公开(公告)号：US20230185718A1

公开(公告)日：2023-06-15

申请号：US17551172

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Anant Vithal Nori ,  Prathmesh Kallurkar ,  Niranjan Kumar Soundararajan ,  Sreenivas Subramoney ,  Lihu Rappoport ,  Hanna Alam ,  Adrian Moga ,  Ronak Singhal

IPC: G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/62

Abstract: Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230091205A1

公开(公告)日：2023-03-23

申请号：US17479582

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Adrian Moga ,  Ugonna Echeruo ,  Eduard Roytman ,  Krishnakanth Sistla ,  Joseph Nuzman ,  Brinda Ganesh ,  Meenakshisundaram Chinthamani ,  Yen-Cheng Liu ,  Sai Prashanth Muralidhara ,  Vivek Kozhikkottu ,  Hanna Alam ,  Narasimha Sridhar Srirangam

IPC: G06F12/0862 ,  G06F13/28

Abstract: Methods and apparatus relating to memory side prefetch architecture for improved memory bandwidth are described. In an embodiment, logic circuitry transmits a Direct Memory Controller Prefetch (DMCP) request to cause a prefetch of data from memory. A memory controller receives the DMCP request and issues a plurality of read operations to the memory in response to the DMCP request. Data read from the memory is stored in a storage structure in response to the plurality of read operations. Other embodiments are also disclosed and claimed.