公开(公告)号：US20220206825A1

公开(公告)日：2022-06-30

申请号：US17134322

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Abhimanyu Kanaiya Varde ,  Karuna Ramkumar ,  Robert Valentine

IPC: G06F9/445 ,  G06F9/30

Abstract: Systems or methods of the present disclosure may provide an initialization technique that enables the initialization of multiple states in an efficient manner. The initialization technique includes a register to track usage of state components of the processor and a decode unit to decode a state initialization instruction. The state initialization instruction indicates that of the state components are to be initialized. The initialization technique also includes an execution unit coupled with the decode unit. The execution unit, in response to the state initialization instruction, is to initialize the state components without reading another state component from memory as part of the initialization.

公开(公告)号：US12112178B2

公开(公告)日：2024-10-08

申请号：US17134322

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Abhimanyu Kanaiya Varde ,  Karuna Ramkumar ,  Robert Valentine

IPC: G06F9/44 ,  G06F9/30 ,  G06F9/445

CPC classification number: G06F9/44505 ,  G06F9/30098 ,  G06F9/30145

Abstract: Systems or methods of the present disclosure may provide an initialization technique that enables the initialization of multiple states in an efficient manner. The initialization technique includes a register to track usage of state components of the processor and a decode unit to decode a state initialization instruction. The state initialization instruction indicates that of the state components are to be initialized. The initialization technique also includes an execution unit coupled with the decode unit. The execution unit, in response to the state initialization instruction, is to initialize the state components without reading another state component from memory as part of the initialization.