公开(公告)号：US09614508B1

公开(公告)日：2017-04-04

申请号：US14958701

申请日：2015-12-03

申请人： Integrated Device Technology, Inc.

发明人： Jagdeep Bal ,  Louis F. Poitras

IPC分类号： H03L7/00 ,  H03K5/14 ,  H03K5/131

CPC分类号： H03K5/14 ,  H03K5/131

摘要： A clock generator having deskewed outputs signals wherein a transit time of each of a plurality of traces coupled to the clock generator outputs are determined and the longest trace is identified as the trace having the longest transit time. A time delay is then added to an output clock signal at each of the clock generator outputs that are not coupled to the longest trace. The addition of the time delay for each of the clock generator outputs is effective in automatically deskewing the clock generator outputs.