公开(公告)号：US12211824B2

公开(公告)日：2025-01-28

申请号：US18130952

申请日：2023-04-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Bäßler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.

公开(公告)号：US20240404925A1

公开(公告)日：2024-12-05

申请号：US18205129

申请日：2023-06-02

Applicant: Infineon Technologies AG

Inventor： Marco Bäßler ,  Martin Haller

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01R12/58

Abstract: A molded power semiconductor package includes a mold compound having first and second opposing main surfaces and an edge between the first and second main surfaces. Power semiconductor dies are embedded in the mold compound. A metallic frame embedded in the mold compound is electrically connected to the power semiconductor dies. Pins protrude from the first main surface of the mold compound, each pin being secured to a respective contact area of the metallic frame that is exposed by an opening in the mold compound at the first main surface. One or more of the openings extends to the edge of the mold compound to form an open channel from each contact area exposed by the one or more of the openings to the edge of the mold compound. Additional package embodiments and methods of production are also described.

公开(公告)号：US20240332136A1

公开(公告)日：2024-10-03

申请号：US18609133

申请日：2024-03-19

Applicant: Infineon Technologies AG

Inventor： Marco Bäßler ,  Michal Chajneta ,  Thorsten Scharf ,  Egbert Lamminger

IPC: H01L23/495

CPC classification number: H01L23/49537 ,  H01L23/49548 ,  H01L23/49575

Abstract: A power semiconductor device includes: at least one substrate; at least one power semiconductor die arranged over the at least one substrate; a first leadframe arranged over the at least one power semiconductor substrate and over the at least one power semiconductor die, the first leadframe being arranged at least partially in a first plane and including one or more connecting portions extending out of the first plane in a first direction; and a second leadframe at least partially arranged in a second plane above or below the first plane and including one or more attachment sites. The one or more connecting portions extend into the second plane at the one or more attachment sites. The one or more connecting portions are arranged at a non-zero distance from the second leadframe, the non-zero distance being bridged by weld seams at the one or more attachment sites.

公开(公告)号：US20240266300A1

公开(公告)日：2024-08-08

申请号：US18107257

申请日：2023-02-08

Applicant: Infineon Technologies AG

Inventor： Marco Bäßler ,  Michael Niendorf

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H05K1/18

CPC classification number: H01L23/562 ,  H01L23/4952 ,  H01L23/49575 ,  H01L23/49861 ,  H05K1/18 ,  H01L23/3121 ,  H01L23/4006 ,  H01L2023/4087 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/48137 ,  H01L2224/48175 ,  H05K2201/09063 ,  H05K2201/09409 ,  H05K2201/1059

Abstract: A power semiconductor module includes: an electrically insulative enclosure; a plurality of power semiconductor dies attached to a substrate inside the electrically insulative enclosure; a lead frame or clip frame disposed above the power semiconductor dies inside the electrically insulative enclosure and electrically connected to the power semiconductor dies; a plurality of contact pins attached to the lead frame or clip frame and protruding through a first side of the electrically insulative enclosure to form an electrical connection interface outside the electrically insulative enclosure; and a plurality of vibration dampeners attached to the lead frame or clip frame. The vibration dampeners protrude through the first side of the electrically insulative enclosure and are separate from the electrical connection interface. The vibration dampeners are configured to dampen vibrations at a circuit board designed to be mounted to the module and do not affect electrical operation of the power semiconductor module.

公开(公告)号：US20230361088A1

公开(公告)日：2023-11-09

申请号：US18130952

申请日：2023-04-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Bäßler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L25/072 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/48

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.