公开(公告)号：US20030089962A1

公开(公告)日：2003-05-15

申请号：US09992344

申请日：2001-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC: H01L021/82 ,  H01L029/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

Abstract translation: 用于熔丝结构的方法和结构包括绝缘体层，穿过绝缘体层延伸到下面的布线层的多个熔丝电极，连接到电极的电镀熔丝元件和界面壁。 保险丝元件位于绝缘体的外部，并且在绝缘体和保险丝元件之间并置有间隙。 界面壁还包括第一侧壁，第二侧壁和内壁，其中内壁设置在间隙内。 熔丝电极彼此直径相对，并且熔丝元件垂直地设置在熔丝电极的上方。 保险丝元件是电镀，无电镀，或是超薄保险丝。

公开(公告)号：US20040259322A1

公开(公告)日：2004-12-23

申请号：US10604028

申请日：2003-06-23

Applicant: International Business Machines Corporation

Inventor： Andrew Lu ,  Donald M. Odiwo ,  Roger J. Yerdon

IPC: H01L021/66

CPC classification number: G03F9/7084 ,  G03F7/70475 ,  Y10S438/975

Abstract: A method of repeatedly exposing a pattern across a wafer in a sequential stepping process is disclosed. The pattern that is exposed includes at least one alignment mark. Each time the exposing process is repeated, the current exposure overlaps a portion of the wafer where the pattern was previously exposed and thereby erases a previously exposed alignment mark by re-exposing an area of the wafer where the previously exposed alignment mark was located. After the exposing process is repeated across the wafer, alignment marks remain only in the last exposed areas of the wafer.

Abstract translation: 公开了一种在连续的步进过程中重复地在晶片上暴露图案的方法。 暴露的图案包括至少一个对准标记。 每次重复暴露过程时，当前的曝光与预先暴露图案的晶片的一部分重叠，从而通过再次暴露先前暴露的对准标记所位于的晶片的区域来擦除先前暴露的对准标记。 在跨晶片重复曝光过程之后，对准标记仅保留在晶片的最后曝光区域中。

公开(公告)号：US20040099963A1

公开(公告)日：2004-05-27

申请号：US10303501

申请日：2002-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karen L. Holloway ,  Andrew Lu ,  Qiang Wu

IPC: H01L023/544

CPC classification number: H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An alignment mark structure for use upon a semiconductor substrate is disclosed. In an exemplary embodiment, the alignment mark structure includes a plurality of segments arranged in an alignment pattern, with each of the plurality of segments being formed from a base pattern created on the substrate. The base pattern includes a plurality of sizes, wherein each of the plurality of sizes of the base pattern is repeated throughout an entire length of each of the plurality of segments.