公开(公告)号：US10891172B2

公开(公告)日：2021-01-12

申请号：US15770790

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Yuping Yang ,  Dujian Wu ,  Shijie Liu ,  Daquan Dong

IPC: G06F9/54 ,  G06F9/4401 ,  G06F9/455 ,  G06F9/48

Abstract: A method includes modifying a basic input/output system (BIOS) to load a virtual general purpose input/output (GPIO) driver in an operating system, the virtual GPIO driver comprising at least one control method to monitor a system control interrupt (SCI) (202). The method can also include detecting the system control interrupt invoking the virtual GPIO driver (204) and executing the control method corresponding to the system control interrupt, the control method to be identified in the modified BIOS (206). Furthermore, the method can include detecting an error from the execution of the control method (208) and modifying an operating system to prevent the error (208), the modification comprising a modification to the control method.

公开(公告)号：US20210397530A1

公开(公告)日：2021-12-23

申请号：US17359404

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Lei Zhu ,  Kevin Yufu Li ,  Shijie Liu ,  Tao Xu

IPC: G06F11/30 ,  G06F11/34 ,  G06F11/07

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to transmit central processing unit (CPU) performance information to an operating system (OS). An apparatus comprising interface circuitry, and processor circuitry to perform at least one of the first operations, the second operations or the third operations to: a CPU detector circuitry to determine a connection status between a first CPU and a second CPU, an encoder circuitry to generate a first CPU identifier for the first CPU port and a second CPU identifier for the second CPU port, a topology identifier circuitry to identify a topology based on the connection status and the CPU identifiers, a transaction performance level (TPL) calculator circuitry to calculate a TPL based on at least one of the connection status, the CPU identifiers, and a topology identifier circuitry, and a TPL transmitter circuitry to transmit the TPL to an OS.

公开(公告)号：US12169460B2

公开(公告)日：2024-12-17

申请号：US18040944

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Shijie Liu ,  Tao Xu ,  Lei Zhu ,  Yufu Li

IPC: G06F13/16 ,  G06F13/10 ,  G06F13/42

Abstract: Embodiments are directed to improving remote traffic performance on cluster-aware processors. An embodiment of a system includes at least one processor package comprising a plurality of processor ports and a plurality of system agents; and a memory device to store platform initialization firmware to cause the processing system to: determine first locations of the plurality of processor ports in the at least one processor package; determine second locations of the plurality of system agents in the at least one processor package; associate each of the processor ports with a set of the plurality of system agents based on the determined first and second locations; and program the plurality of system agents with the associated processor port for the respective system agent.

公开(公告)号：US20240281315A1

公开(公告)日：2024-08-22

申请号：US18570493

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Shijie Liu ,  Tao Xu ,  Lei Zhu ,  Kevin Yufu LI

IPC: G06F11/07

CPC classification number: G06F11/076 ,  G06F11/0745 ,  G06F11/0793

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that perform runtime recovery of processor links. An example non-transitory computer readable medium comprises instructions that, when executed, causes a machine to at least determine an onset of an error based on health of a central processor unit (CPU) port, calculate a figure of merit (FOM) yield for each of a plurality of adaptation tasks performed on a lane of the CPU port using a first preset coefficient of a plurality of preset coefficients, select a preset coefficient based on the calculated FOM, and trigger a link recovery mechanism, using the selected preset coefficient to initiate a link recovery process on the CPU port.

公开(公告)号：US20240241805A1

公开(公告)日：2024-07-18

申请号：US18560270

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Tao Xu ,  Shijie Liu ,  Kevin Yufu Li ,  Lei Zhu ,  Sarathy Jayakumar

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G06F2201/85

Abstract: A disclosed example includes setting a corrected error threshold value for a memory rank; recording, in a corrected error bank record memory structure, corrected errors for memory banks in the memory rank; maintaining, in the corrected error bank record memory structure, counts of the corrected errors for the memory banks; and notifying runtime error handling circuitry in response to at least one of the counts of the corrected errors satisfying a threshold value.