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公开(公告)号：US09480162B2
公开(公告)日：2016-10-25
申请号：US14691468
申请日：2015-04-20
Applicant: INTEL CORPORATION
Inventor： Md Altaf Hossain , Jin Zhao , John T. Vu
CPC classification number: H05K1/183 , H01L2224/16225 , H01L2924/15311 , H05K1/0326 , H05K1/113 , H05K1/115 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/32 , H05K3/42 , H05K2201/09545 , H05K2201/09709 , H05K2201/0989 , H05K2201/10734 , Y10T29/4913
Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.
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Patent Agency Ranking
公开(公告)号：US11538753B2
公开(公告)日：2022-12-27
申请号：US16465255
申请日：2016-12-30
Applicant: Intel Corporation
Inventor： MD Altaf Hossain , Ankireddy Nalamalpu , Scott Gilbert , Jin Zhao
IPC: H01L23/48 , H01L23/528 , H01L23/498
Abstract: An electronic chip, system, and method includes a power block including a power source configured to provide power to components of the electronic chip and a relay circuit coupled to the power source and a ground plane. The electronic chip further includes chip package having a first major side and a second major side, the power block secured to the second major side, the chip package comprising electrical connections, disposed on the second major side, to be secured with respect to a circuit board, and interconnect circuitry, electrically coupling the power block to ground, comprising a plurality of conductive layers, a conductive through hole, electrically connecting a first pair of the plurality of conductive layers, having a first width, and a via, electrically connecting a second pair of the plurality of conductive layers, having a second width less than the first width.
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公开(公告)号：US10159152B2
公开(公告)日：2018-12-18
申请号：US14977321
申请日：2015-12-21
Applicant: Intel Corporation
Inventor： Ladd D. Campbell , Scott M. Mokler , Juan Landeros, Jr. , Michael J. Hill , Jin Zhao
Abstract: Embodiments of the invention include a printed circuit board (PCB) assembly that includes advanced component in cavity (ACC) technology and methods of forming such PCB assemblies. In one embodiment, the PCB assembly may include a PCB that has a cavity formed on a first surface of the PCB. A plurality of contacts may be formed in the cavity. The cavity provides a location where components may be electrically coupled to the PCB. Additionally, a package that is mounted to the PCB may extend over the cavity. Since the package passes directly over the component, the components may be used to electrically couple the package to one or more of the contacts formed in the cavity. Accordingly, embodiments of the invention allow for the surface area used for components to be reduced, and also improves electrical performance of the PCB assembly by positioning the components proximate to the package.
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公开(公告)号：US20190333854A1
公开(公告)日：2019-10-31
申请号：US16465255
申请日：2016-12-30
Applicant: Intel Corporation
Inventor： MD Altaf Hossain , Ankireddy Nalamalpu , Scott Gilbert , Jin Zhao
IPC: H01L23/528 , H01L23/498 , H01L23/48
Abstract: An electronic chip, system, and method includes a power block including a power source configured to provide power to components of the electronic chip and a relay circuit coupled to the power source and a ground plane. The electronic chip further includes chip package having a first major side and a second major side, the power block secured to the second major side, the chip package comprising electrical connections, disposed on the second major side, to be secured with respect to a circuit board, and interconnect circuitry, electrically coupling the power block to ground, comprising a plurality of conductive layers, a conductive through hole, electrically connecting a first pair of the plurality of conductive layers, having a first width, and a via, electrically connecting a second pair of the plurality of conductive layers, having a second width less than the first width.
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公开(公告)号：US20150230338A1
公开(公告)日：2015-08-13
申请号：US14691468
申请日：2015-04-20
Applicant: INTEL CORPORATION
Inventor： Md Altaf Hossain , Jin Zhao , John T. Vu
CPC classification number: H05K1/183 , H01L2224/16225 , H01L2924/15311 , H05K1/0326 , H05K1/113 , H05K1/115 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/32 , H05K3/42 , H05K2201/09545 , H05K2201/09709 , H05K2201/0989 , H05K2201/10734 , Y10T29/4913
Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例涉及具有诸如电感器，电容器，电阻器和相关技术和配置的集成无源器件的电路板。 在一个实施例中，一种装置包括具有与第一表面相对的第一表面和第二表面的电路板，以及与电路板成一体的无源器件，该无源器件具有被配置为与管芯的电力耦合的输入端子， 与输入端子电耦合的输出端子以及设置在电路板的第一表面和第二表面之间的电气路由特征，并且与输入端子和输出端子耦合以在输入端子和输出端子之间布置电力 ，其中所述输入端子包括被配置为接收包括所述管芯的封装组件的焊球连接的表面。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US09035194B2
公开(公告)日：2015-05-19
申请号：US13664264
申请日：2012-10-30
Applicant: INTEL CORPORATION
Inventor： M D Altaf Hossain , Jin Zhao , John T. Vu
CPC classification number: H05K1/183 , H01L2224/16225 , H01L2924/15311 , H05K1/0326 , H05K1/113 , H05K1/115 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/32 , H05K3/42 , H05K2201/09545 , H05K2201/09709 , H05K2201/0989 , H05K2201/10734 , Y10T29/4913
Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例涉及具有诸如电感器，电容器，电阻器和相关技术和配置的集成无源器件的电路板。 在一个实施例中，一种装置包括具有与第一表面相对的第一表面和第二表面的电路板，以及与电路板成一体的无源器件，该无源器件具有被配置为与管芯的电力耦合的输入端子， 与输入端子电耦合的输出端子以及设置在电路板的第一表面和第二表面之间的电气路由特征，并且与输入端子和输出端子耦合以在输入端子和输出端子之间布置电力 ，其中所述输入端子包括被配置为接收包括所述管芯的封装组件的焊球连接的表面。 可以描述和/或要求保护其他实施例。
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