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1.发明授权Addition circuit for the digital codes generated in accordance with a nonlinear compression law 失效根据非线性压缩法产生的数字代码的附加电路
公开(公告)号：US3575591A
公开(公告)日：1971-04-20
申请号：US3575591D
申请日：1968-09-27
Applicant: INT STANDARD ELECTRIC CORP
CPC classification number: H04M3/561
Abstract: There is disclosed an arrangement including a translator to derive two linear code signals from two compressed code signals and compressing the resultant sum of the two linear code signals in the translator after addition in an adder circuit. The translator comprises a shift register operating in two directions and a counter.
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