公开(公告)号：US3683163A

公开(公告)日：1972-08-08

申请号：US3683163D

申请日：1969-08-20

Applicant: INT COMPUTERS LTD

Inventor： HANSLIP TREVOR WILLIAM

IPC: G06F7/50 ,  G06F7/505 ,  G06F7/28 ,  G06F7/385

CPC classification number: G06F7/505 ,  G06F7/494 ,  G06F2207/3816 ,  G06F2207/4924

Abstract: A technique for adding fields or portions in a fixed word adding system with carry-in and carry-out signals being as if two complete words are added together. A masking register causes two logic circuits to pass particular fields of corresponding words in two word registers. The logic circuits operate to fill the digits of one word outside of the field of that word with binary ''''1'''' signals and corresponding digits of the other word with binary O''s. The sum of each digit which appears in the adder is a binary ''''1'''' so that a carry-in signal may be injected at the lowest order bit position of the adder and extracted from the highest order bit position of the adder in a normal manner. The masking register controls a further logic circuit so that only the added fields are read out of the adder.

Abstract translation: 在具有进位和执行信号的固定字添加系统中添加字段或部分的技术就好像将两个完整的字相加在一起。 屏蔽寄存器使两个逻辑电路通过两个字寄存器中相应字的特定字段。 逻辑电路用二进制“1”信号和具有二进制O的另一个字的对应数字填充该字的字外的一个字的数字。 出现在加法器中的每个数字的和是二进制“1”，使得可以在加法器的最低位位置处注入进位信号，并以正常方式从加法器的最高位位置提取 。 屏蔽寄存器控制另一个逻辑电路，使得仅从加法器读出相加的场。