公开(公告)号：US3846759A

公开(公告)日：1974-11-05

申请号：US27470372

申请日：1972-07-24

Applicant: INT COMPUTERS LTD

Inventor： DRAKE J ,  PAYNE A ,  REICHERT A

IPC: G06F7/02 ,  G06F13/12 ,  G06F9/00

CPC classification number: G06F7/02 ,  G06F13/126

Abstract: A data processor is described particularly suited to provide a universal link between a peripheral mechanism and a central computer. The arrangement provides, in addition to an input selection and masking unit and a selective masking output unit, a processing unit for performing logic operations on input information relating to, e.g., incoming and status signals relating to the associated peripheral mechanism in order to derive an output signal pattern for controlling the actuation of the peripheral. In order to carry out a program of stored instructions, each of which specifies a function to be performed, it is frequently necessary that data resulting from the performance of preceding functions is required to undergo processing, for example, comparison with, or modification in the light of, a second item of data. A double set of registers is provided and the processing unit is able, under control of some functional instructions to address a single register in each set so that the contents of both addressed registers are rendered available concurrently on a single program step. There is also provision for using one of the specified addresses as the destination for the result of the prescribed function.

Abstract translation: 描述数据处理器特别适合于在外围机构和中央计算机之间提供通用连接。 除了输入选择和掩蔽单元以及选择性屏蔽输出单元之外，该装置还提供一个处理单元，用于对输入信息执行逻辑运算，例如与相关联的外围机制相关的输入信号和状态信号，以便导出 用于控制外围设备致动的输出信号模式。 为了执行存储指令的程序，每个程序指定要执行的功能，通常需要由执行前述功能所得到的数据进行处理，例如与 第二项数据。 提供了一组双寄存器，并且处理单元能够在一些功能指令的控制下对每组中的单个寄存器进行寻址，使得两个寻址的寄存器的内容在单个程序步骤中同时呈现。 还规定使用指定地址之一作为规定功能的结果的目的地。