公开(公告)号：US3703705A

公开(公告)日：1972-11-21

申请号：US3703705D

申请日：1970-12-31

Applicant: IBM

Inventor： PATEL ARVIND M

IPC: H03M13/15 ,  G06F11/12

CPC classification number: H03M13/15

Abstract: A linear feedback shift register for operating on a plurality f of parallel inputs according to a generator polynomial to produce encoding and decoding is provided having a plurality r of shift register stages X0 . . . Xr 1 each corresponding to one of the terms in the generator polynomial. A first plurality of modulo 2 addition means connect, for modulo 2 addition, each of said f data bit inputs Zt f 1, Zt f 2, . . . , Zt 1, Zt of the shift register to the output of an individual one of the last f register stages Xr f, Xr f 1, . . . , Xr 1 according to the relationship Zt f 1 to Xr f, Zt f 2 to Xr f 1, . . . , Zt to Xr 1. A second plurality of modulo 2 addition means are connected to the respective inputs of the first Xr f 2 shift register stages. The first feedback connection from the output of each of said first plurality of modulo 2 addition means in said f shift register stages is connected to each of two preceding second modulo 2 addition means in accordance with the relationship Xr f 1 to X1 and X2; Xr f 2 to X2 and X3; Xr 1 to Xr f 1 and Xr f 2. A third modulo 2 addition means connects each output of the first plurality of modulo 2 addition means to the register stages determined in accordance with the non-zero coefficients in the generator polynomial.

Abstract translation: 提供一种线性反馈移位寄存器，用于根据生成多项式在并行输入的多个f上操作以产生编码和解码，其具有多个移位寄存器级X0。 。 。 Xr-1各自对应于生成多项式中的一个项。 第一多个模2加法装置连接，用于模2加法，每个所述f数据比特输入Zt + f-1，Zt + f-2。 。 。 ，Zt + 1，Zt到最后f个寄存器级Xr-f，Xr-f + 1中的一个的输出。 。 。 ，Xr-1，根据关系Zt + f-1〜Xr-f，Zt + f-2〜Xr-f + 1。 。 。 Zt到Xr-1。 第二组多个模2加法装置连接到第一Xr-f + 2移位寄存器级的相应输入端。 根据Xr-f + 1至X1和X2的关系，将所述f个移位寄存器级中的所述第一多模2加法装置的每一个的输出的第一反馈连接连接到前两个第二模2加法装置中的每一个 ; Xr-f + 2〜X2和X3; Xr-1至Xr-f + 1和Xr-f + 2。 第三模2加法装置将第一多个模2加法装置的每个输出连接到根据生成多项式中的非零系数确定的寄存器级。

公开(公告)号：US3504356A

公开(公告)日：1970-03-31

申请号：US3504356D

申请日：1967-01-13

Applicant: IBM

Inventor： PATEL ARVIND M ,  SUMILAS JOHN W

IPC: G11C11/06 ,  H03H7/32 ,  G11C7/06

CPC classification number: G11C11/06007 ,  H03H7/32

公开(公告)号：US3913068A

公开(公告)日：1975-10-14

申请号：US49319574

申请日：1974-07-30

Applicant: IBM

Inventor： PATEL ARVIND M

IPC: G06F11/10 ,  G06F12/16 ,  G11B20/12 ,  G11B20/18 ,  H03M13/00 ,  G06F11/12

CPC classification number: G11B20/1809 ,  G11B20/1803

Abstract: This specification describes an error correction scheme for digital information serially recorded on a magnetic medium; for example, in stripes oriented diagonally across magnetic tape. The digital information is arranged in segments made up of a set of data sections and two subfield code sections generated on a byte for byte basis from the set of data sections in accordance with Patel U.S. Pat. No. 3,745,528. Thus the first byte of each of the subfield code sections is generated from the first bytes in all the data sections, the second byte of each subfield code section is generated from the second bytes in all the data sections and so on. Each of the sections in the segment is terminated with a synchronization burst. With this arrangement up to two full sections of any data segment can be corrected using these subfield code sections.

公开(公告)号：US3876978A

公开(公告)日：1975-04-08

申请号：US36693673

申请日：1973-06-04

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  HSIAO MU-YUE ,  PATEL ARVIND M

IPC: G06F12/16 ,  G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  G11B27/36 ,  G06K5/02

CPC classification number: G06F11/1076 ,  G06F11/1008

Abstract: This specification describes a system for preventing the catastrophic loss of data in one storage unit of a storage system comprised of a plurality of such storage units. In this system one of the plurality of storage units is used to store parity bits for the storage system, bit position by bit position. To be more specific, if the data in each of the storage units is considered to be a linear string of bits the storage unit containing the parity bits would contain a parity or Exclusive OR sum of all the first bits of all the storage units or, in a more general case, the j.sup.th bit of the check storage unit is the parity or Exclusive OR sum of all the j bits of all the storage units.

公开(公告)号：US3868632A

公开(公告)日：1975-02-25

申请号：US39013673

申请日：1973-08-20

Applicant: IBM

Inventor： HONG SE J ,  PATEL ARVIND M

IPC: G06F12/16 ,  G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  G06F11/12

CPC classification number: G11B20/1833

Abstract: Error correcting apparatus is provided for correcting plural channels in error in a parallel channel information system. The information is encoded in a cross-channel direction as well as along the channel length. The encoded message after storage or transmission is decoded in the cross-channel direction and error correction provided in the in-channel direction in a given number of indicated channels. Orthogonally symmetrical redundancy enhances error correction while tending to minimize hardware. Plural independent codes interact to correct the plural channels in error. The error correcting capabilities of the codes may be matched, no limitation thereto intended.