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公开(公告)号：US11764944B2
公开(公告)日：2023-09-19
申请号：US17566337
申请日：2021-12-30
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Haohao Liao , Zhiwei Shang , Yin Tan
IPC: H04L9/00
CPC classification number: H04L9/008 , H04L2209/125
Abstract: A field-programmable gate array (FPGA) cluster, comprising a plurality of FPGA devices, can be used to accelerate homomorphic encryption functionality. In particular, the FPGA cluster can accelerate the relinearization process used in homomorphic encryption by using multiple FPGA devices to perform portions of the relinearization process in parallel. Further, the use of the FPGA cluster provides sufficient memory resources to allow data used by the relinearization process, namely the keyswitch keys, to be stored on-chip.
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公开(公告)号：US11451375B2
公开(公告)日：2022-09-20
申请号：US17038998
申请日：2020-09-30
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Priya Soundararajan , Zhijun Mo , Zhiwei Shang
Abstract: The disclosed systems, and methods are directed to a method for Privacy Preserving Inference (PPI) comprising receiving a first set of matrix information from a client device, generating kc−1 matrices by operating a first CSPRNG associated with the server with kc−1 seeds, computing inferences from the set of kc matrices, generating a matrix Ss, generating ks−1 random matrices, computing a matrix Yks in accordance with the inference matrix Y, the matrix Ss and the ks−1 random matrices, transmitting a second set of matrix information to the client device, the second set of matrix information includes ks−1 seeds corresponding to the ks−1 random matrices and the matrix Yks, receiving a matrix U from the client device, and computing an inference value y from the matrix U.
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3.发明公开公开(公告)号：US20230216656A1
公开(公告)日：2023-07-06
申请号：US17566783
申请日：2021-12-31
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Haohao Liao , Zhiwei Shang , Yin Tan
CPC classification number: H04L9/008 , H04L9/3093 , G06F7/728 , G06F17/16
Abstract: A low latency relinearization process can be performed in an FPGA cluster for accelerating homomorphic encryption. The low-latency process performs an early calculation of matrix rows to make the summation result available earlier in the relinearization to reduce waiting of subsequent operations.
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Patent Agency Ranking
公开(公告)号：US11687534B2
公开(公告)日：2023-06-27
申请号：US17350549
申请日：2021-06-17
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Zhiwei Shang , Zhijun Mo
IPC: G06F16/2455 , G06F21/62
CPC classification number: G06F16/2455 , G06F21/6245
Abstract: The disclosed systems and methods are directed to detecting sensitive data on a computing device. This includes matching predetermined keywords in input data, to determine data in vicinities of matched keywords in the input data in which sensitive data is likely to be found, and matching predefined patterns associated with sensitive data to the data in vicinities of matched keywords to detect sensitive data. Matching the predetermined keywords occurs prior to matching the predefined patterns, and the data in vicinities of matched keywords is substantially shorter than the input data.
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公开(公告)号：US08947174B2
公开(公告)日：2015-02-03
申请号：US14195409
申请日：2014-03-03
Applicant: Huawei Technologies Co., Ltd.
Inventor： Haizhao Wang , Guangfu Si , Naier Meng , Bo Yang , Puke Zhou , Shengxiang Guo , Yi Zhang , Weihua Sun , Jianjun Zhou , Ke Zhang , Hao Li , Zhiwei Shang , Runxiao Zhang
CPC classification number: H03H7/463 , H01P1/213 , H01P1/2136 , H01P1/2138 , H01P11/007 , H05K7/20409
Abstract: The present disclosure relates to telecommunication, and in particular, to a base station Radio Frequency (RF) duplexer, an RF module, and an RF system. A base station RF apparatus provided herein includes: an enclosure, an intermediate RF processing unit, and a duplexer. The enclosure is located on the duplexer; the intermediate RF processing unit is located inside a cavity enclosed by the enclosure and the duplexer, or on the duplexer; a duplexer cavity and a heat dissipation part exist on the surface of the duplexer; the opening of the duplexer cavity is opposite to or against the enclosure; the heat dissipation part is designed to dissipate heat of the intermediate RF processing unit; and the duplexer is integrally molded. The foregoing technical solution requires no external fasteners, reduces the time of production and assembly. In addition, waterproof design and shielding design are not required, and thus improves the reliability.
Abstract translation: 本公开涉及电信，特别是涉及基站射频（RF）双工器，RF模块和RF系统。 本文提供的基站RF装置包括：外壳，中间RF处理单元和双工器。 外壳位于双工器上; 中间RF处理单元位于由外壳和双工器包围的腔内，或位于双工器上; 在双工器的表面上存在双工器腔和散热部分; 双工器腔的开口与外壳相对或相对; 散热部分设计用于散发中间RF处理单元的热量; 双工器整体模制。 上述技术方案不需要外部紧固件，减少生产和组装的时间。 另外，不需要防水设计和屏蔽设计，从而提高了可靠性。
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6.发明授权公开(公告)号：US11902414B2
公开(公告)日：2024-02-13
申请号：US17566783
申请日：2021-12-31
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Haohao Liao , Zhiwei Shang , Yin Tan
CPC classification number: H04L9/008 , G06F7/728 , G06F17/16 , H04L9/3093
Abstract: A low latency relinearization process can be performed in an FPGA cluster for accelerating homomorphic encryption. The low-latency process performs an early calculation of matrix rows to make the summation result available earlier in the relinearization to reduce waiting of subsequent operations.
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7.发明授权公开(公告)号：US11861923B2
公开(公告)日：2024-01-02
申请号：US17566817
申请日：2021-12-31
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Zhiwei Shang , Tongyu Ge , Zhijun Mo
IPC: G06V30/19 , H04N1/44 , G06V30/12 , G06V30/164
CPC classification number: G06V30/19093 , G06V30/12 , G06V30/164 , H04N1/448
Abstract: The present disclosure describes a method, an apparatus, and a non-transitory computer-readable medium for detecting sensitive text information such as privacy-related text information from a signal and modifying the signal by removing the detected sensitive text information therefrom. The apparatus receives the signal such as an image, a video clip, or an audio clip, and recognizes a text string therefrom. The apparatus then detects, from the text string, a substring based on a similarity between the substring and a regular expression, and modifies the signal by removing information related to the detected substring from the signal.
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8.发明公开公开(公告)号：US20230216655A1
公开(公告)日：2023-07-06
申请号：US17566337
申请日：2021-12-30
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Haohao Liao , Zhiwei Shang , Yin Tan
IPC: H04L9/00
CPC classification number: H04L9/008 , H04L2209/125
Abstract: A field-programmable gate array (FPGA) cluster, comprising a plurality of FPGA devices, can be used to accelerate homomorphic encryption functionality. In particular, the FPGA cluster can accelerate the relinearization process used in homomorphic encryption by using multiple FPGA devices to perform portions of the relinearization process in parallel. Further, the use of the FPGA cluster provides sufficient memory resources to allow data used by the relinearization process, namely the keyswitch keys, to be stored on-chip.
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