公开(公告)号：US10586590B2

公开(公告)日：2020-03-10

申请号：US15822850

申请日：2017-11-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yide Zhang ,  Zhigang Zeng ,  Yidong Zhu ,  Mingfu Cao ,  Junfeng Zhao

IPC: G11C11/00 ,  G11C13/00 ,  G11C8/16

Abstract: A circuit, where a first end of a resistive random access memory (RRAM) included in the circuit includes a first end of the circuit, and a second end of the RRAM is coupled to a first end of a first switch and a first end of a second switch, a second end of the first switch includes a second end of the circuit, and a first control end of the first switch and a second control end of the second switch are configured to make the first switch closed and the second switch open at the same time. Therefore, a working status of the RRAM is flexibly controlled.

公开(公告)号：US20180082738A1

公开(公告)日：2018-03-22

申请号：US15822850

申请日：2017-11-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yide Zhang ,  Zhigang Zeng ,  Yidong Zhu ,  Mingfu Cao ,  Junfeng Zhao

IPC: G11C13/00

Abstract: A circuit, where a first end of a resistive random access memory (RRAM) included in the circuit includes a first end of the circuit, and a second end of the RRAM is coupled to a first end of a first switch and a first end of a second switch, a second end of the first switch includes a second end of the circuit, and a first control end of the first switch and a second control end of the second switch are configured to make the first switch closed and the second switch open at the same time. Therefore, a working status of the RRAM is flexibly controlled.