公开(公告)号：US20230049723A1

公开(公告)日：2023-02-16

申请号：US17976207

申请日：2022-10-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xi Qin ,  Xun Gu ,  Yu Tian

IPC: H01L27/02 ,  H01L29/78

Abstract: This application provides an integrated circuit, including a first MOS transistor. A first effective gate and a second effective gate are disposed in the first MOS transistor, and a first redundant gate is disposed between the first effective gate and the second effective gate. The first effective gate, the second effective gate, and the first redundant gate cover a plurality of fins arranged in parallel. The first effective gate and the second effective gate are connected to a gate terminal of the first MOS transistor. Fins on both sides of the first effective gate and fins on both sides of the second effective gate are respectively connected to a source terminal and a drain terminal of the first MOS transistor. The first redundant gate is connected to a redundant potential or suspended.