Abstract:
A method for sending service information includes: judging whether a current ACM profile identifier (profile ID) is consistent with an ACM profile ID recorded in separately-stored coding and modulation information; when the current ACM profile ID is consistent with the ACM profile ID recorded in the separately-stored coding and modulation information, coding and modulating the service information according to the coding and modulation information; when the current ACM profile ID is inconsistent with the ACM profile ID recorded in the separately-stored coding and modulation information, coding and modulating the service information according to an ACM profile table; and sending the coded and modulated service information, where the coded and modulated service information carries the current ACM profile ID.
Abstract:
A method for sending service information includes: judging whether a current ACM profile identifier (profile ID) is consistent with an ACM profile ID recorded in separately-stored coding and modulation information; when the current ACM profile ID is consistent with the ACM profile ID recorded in the separately-stored coding and modulation information, coding and modulating the service information according to the coding and modulation information; when the current ACM profile ID is inconsistent with the ACM profile ID recorded in the separately-stored coding and modulation information, coding and modulating the service information according to an ACM profile table; and sending the coded and modulated service information, where the coded and modulated service information carries the current ACM profile ID.
Abstract:
Embodiments of the present invention disclose a CDR circuit and a terminal, where the CDR circuit is configured to perform clock synchronization in a terminal with EEE function, and the CDR circuit includes: a phase detector, a first phase signal selector, a loop filter, a numerical controlled oscillator, a second phase signal selector, a phase signal generator, and a state machine. In the embodiments of the present invention, after the terminal enters a REFRESH state from a QUIET state, the CDR circuit can implement clock synchronization with a peer end without waiting for the loop filter and the numerical controlled oscillator to be converged, but the phase signal generator generates a phase signal satisfying a preset clock synchronization condition, and the second phase signal selector selects the phase signal satisfying the preset clock synchronization condition as the phase selection signal of the CDR.