公开(公告)号：US10164613B2

公开(公告)日：2018-12-25

申请号：US15676788

申请日：2017-08-14

Applicant: Huawei Technologies Co., Ltd.

Inventor： Qi Chen ,  Jianfu Zhong ,  Qiuling Zeng ,  Yu Xia

IPC: H03K3/012 ,  H03K5/159

Abstract: A phase-inverted clock generation circuit is provided, where sources of a first PMOS and a second PMOS are connected to a power source, drains of the first PMOS and the second PMOS are connected to a source of a third PMOS, and a drain of the third PMOS is connected to a drain of a third NMOS; and the drain of the third PMOS is connected to a drain of a second NMOS, a source of the second NMOS is connected to a drain of a first NMOS, and a source of the first NMOS and a source of the third NMOS.

公开(公告)号：US20180048297A1

公开(公告)日：2018-02-15

申请号：US15676788

申请日：2017-08-14

Applicant: Huawei Technologies Co., Ltd.

Inventor： Qi Chen ,  Jianfu Zhong ,  Qiuling Zeng ,  Yu Xia

IPC: H03K3/012 ,  H03K5/159

CPC classification number: H03K3/012 ,  H03K5/159

Abstract: A phase-inverted clock generation circuit is provided, where sources of a first PMOS and a second PMOS are connected to a power source, drains of the first PMOS and the second PMOS are connected to a source of a third PMOS, and a drain of the third PMOS is connected to a drain of a third NMOS; and the drain of the third PMOS is connected to a drain of a second NMOS, a source of the second NMOS is connected to a drain of a first NMOS, and a source of the first NMOS and a source of the third NMOS.