-
公开(公告)号：US20220245218A1
公开(公告)日：2022-08-04
申请号：US17725492
申请日：2022-04-20
发明人： Hu Liu , Heng Liao , Jiajin Tu , Honghui Yuan , Hou Fun Lam , Fan Zhu
IPC分类号： G06F17/16
摘要： Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.
-
公开(公告)号：US11823303B2
公开(公告)日：2023-11-21
申请号：US16932768
申请日：2020-07-19
发明人： Luping Cui , Jiajin Tu , Hu Liu , Honghui Yuan , Heng Liao , Hou Fun Lam , Bing Li
CPC分类号： G06T1/20 , G06F17/16 , G06N3/02 , G06V10/454 , G06V10/82
摘要： A data processing method and apparatus are disclosed. In various embodiments, R groups of proposal region sequences are obtained. Each group of proposal region sequence includes a plurality of proposal regions. In those embodiments, a VRPAC instruction is invoked to calculate an area of each proposal region in each group of proposal region sequence. For a jth group of proposal region sequence in the R groups of proposal region sequences, a VIOU instruction and a VAADD instruction are invoked to determine j suppression matrices of the jth group of proposal region sequence and determine a suppression vector of the jth group of proposal region sequence based on the j suppression matrices. In those embodiments, an unsuppressed proposal region is determined based on a suppression vector of each group of proposal region sequence.
-
公开(公告)号：US11422861B2
公开(公告)日：2022-08-23
申请号：US17107173
申请日：2020-11-30
发明人： Xiong Gao , Wei Li , Ming Zheng , Hou Fun Lam
摘要： A data processing method implemented by a computer device, includes generating a target task including a buffer application task or a buffer release task, when the target task is the buffer application task, a first buffer corresponding to the buffer application task is used when the second task is executed, or when the target task is the buffer release task, a second buffer corresponding to the buffer release task is used when the first task is executed, obtaining a buffer entry corresponding to the target task after a preceding task of the target task is executed and before a successive task of the target task is executed, where the buffer entry includes a memory size of a buffer corresponding to the target task, a memory location of the buffer, and a memory address of the buffer, and executing the target task to apply for or release the buffer.
-
公开(公告)号：US20240028423A1
公开(公告)日：2024-01-25
申请号：US18477117
申请日：2023-09-28
发明人： Xiangyi Zhu , Hou Fun Lam
IPC分类号： G06F9/52
CPC分类号： G06F9/52
摘要： In a synchronization method, a first processor creates a first synchronization object for a first synchronization event. The first synchronization object includes an identifier of a first synchronization register. A value of the first synchronization register includes a first value or a second value. The first value is used to indicate that the first synchronization event does not occur, and the second value is used to indicate that the first synchronization event occurs. The first processor includes a first CPU. The second processor determines, based on the value of the first synchronization register, whether the first synchronization event occurs. The second processor includes a first NPU.
-
公开(公告)号：US20220365822A1
公开(公告)日：2022-11-17
申请号：US17878401
申请日：2022-08-01
发明人： Xiong Gao , Wei Li , Ming Zheng , Hou Fun Lam
摘要： A data processing method implemented by a computer device, includes generating a target task including a buffer application task or a buffer release task, when the target task is the buffer application task, a first buffer corresponding to the buffer application task is used when the second task is executed, or when the target task is the buffer release task, a second buffer corresponding to the buffer release task is used when the first task is executed, obtaining a buffer entry corresponding to the target task after a preceding task of the target task is executed and before a successive task of the target task is executed, where the buffer entry includes a memory size of a buffer corresponding to the target task, a memory location of the buffer, and a memory address of the buffer, and executing the target task to apply for or release the buffer.
-
公开(公告)号：US20210081249A1
公开(公告)日：2021-03-18
申请号：US17107173
申请日：2020-11-30
发明人： Xiong Gao , Wei Li , Ming Zheng , Hou Fun Lam
摘要： A data processing method implemented by a computer device, includes generating a target task including a buffer application task or a buffer release task, when the target task is the buffer application task, a first buffer corresponding to the buffer application task is used when the second task is executed, or when the target task is the buffer release task, a second buffer corresponding to the buffer release task is used when the first task is executed, obtaining a buffer entry corresponding to the target task after a preceding task of the target task is executed and before a successive task of the target task is executed, where the buffer entry includes a memory size of a buffer corresponding to the target task, a memory location of the buffer, and a memory address of the buffer, and executing the target task to apply for or release the buffer.
-
公开(公告)号：US12073261B2
公开(公告)日：2024-08-27
申请号：US18477117
申请日：2023-09-28
发明人： Xiangyi Zhu , Hou Fun Lam
CPC分类号： G06F9/52
摘要： In a synchronization method, a first processor creates a first synchronization object for a first synchronization event. The first synchronization object includes an identifier of a first synchronization register. A value of the first synchronization register includes a first value or a second value. The first value is used to indicate that the first synchronization event does not occur, and the second value is used to indicate that the first synchronization event occurs. The first processor includes a first CPU. The second processor determines, based on the value of the first synchronization register, whether the first synchronization event occurs. The second processor includes a first NPU.
-
公开(公告)号：US11941434B2
公开(公告)日：2024-03-26
申请号：US17097211
申请日：2020-11-13
发明人： Wei Li , Xiong Gao , Hou Fun Lam , Tao Ma
CPC分类号： G06F9/4881 , G06F9/3838
摘要： A task processing method, a processing apparatus, and a computer system are provided. Implementation of the method includes: generating, by a first processing apparatus, a plurality of tasks, and determining task description information of the plurality of tasks, where the task description information of the plurality of tasks is used to indicate a dependency relationship between the plurality of tasks; sending an instruction to a second processing apparatus, where the instruction includes the plurality of tasks and the task description information of the plurality of tasks; and receiving the instruction, and processing the plurality of tasks based on the dependency relationship between the plurality of tasks. The method can effectively reduce a waiting delay, fully exploit a computing capability of an acceleration chip, and improve task processing efficiency.
-
公开(公告)号：US11934481B2
公开(公告)日：2024-03-19
申请号：US17725492
申请日：2022-04-20
发明人： Hu Liu , Heng Liao , Jiajin Tu , Honghui Yuan , Hou Fun Lam , Fan Zhu
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.
-
公开(公告)号：US11334648B2
公开(公告)日：2022-05-17
申请号：US16915915
申请日：2020-06-29
发明人： Hu Liu , Heng Liao , Jiajin Tu , Honghui Yuan , Hou Fun Lam , Fan Zhu
IPC分类号： G06F17/16
摘要： Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.021 秒)
