公开(公告)号：US20240355372A1

公开(公告)日：2024-10-24

申请号：US18759492

申请日：2024-06-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Leibin NI ,  Zhihang WU ,  Wei WU ,  Song MA

IPC: G11C7/16 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/16 ,  G11C7/1012 ,  G11C7/12

Abstract: Examples of circuits, multiplier-adders, and circuit optimization methods are described. One example circuit includes a digital addition circuit and an analog addition circuit. The digital addition circuit is configured to perform bitwise digital accumulation on bits that belong to a first bit position range and that are in a plurality of groups of partial products. The plurality of groups of partial products are obtained by multiplying a plurality of first values by a plurality of second values. The first bit position range refers to S bit positions of a product value of one of the first values and one of the second values. S is a positive integer. The product value is obtained by performing bitwise accumulation after a group of partial products are shifted.