公开(公告)号：US09906230B2

公开(公告)日：2018-02-27

申请号：US15099108

申请日：2016-04-14

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Dmitry Petrov ,  Haitao Mei

IPC分类号： H03L7/099 ,  H03L7/089 ,  H03L7/091 ,  H03B5/12

CPC分类号： H03L7/099 ,  G06F1/022 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03K3/0322 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/0995 ,  H03L7/16

摘要： The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase detector, the phase detector generating a primary control signal to adjust the variable frequency oscillator; and a secondary control subsystem having an analog-to-digital converter and a digital-to-analog converter connected in series to receive the primary control signal and generate a secondary control signal also connected to independently adjust the variable frequency oscillator.

公开(公告)号：US11245407B2

公开(公告)日：2022-02-08

申请号：US16925657

申请日：2020-07-10

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Dmitry Petrov ,  Ehud Nir

IPC分类号： H03L7/23 ,  H03L7/093 ,  H03L7/089 ,  H03L7/197 ,  H03L7/081

摘要： The disclosed systems, structures, and methods are directed to a low jitter phase-lock loop (PLL) based frequency synthesizer, comprising a first frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a voltage control oscillator (VCO), a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises a quadrature generator, an input conditioner, a phase rotator, a current mode logic (CML), and a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector.