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公开(公告)号：US12050964B1
公开(公告)日：2024-07-30
申请号：US17010944
申请日：2020-09-03
Applicant: Google LLC
Inventor： Yuezhen Niu , Vadim Smelyanskiy , Sergio Boixo Castrillo
Abstract: The present disclosure provides systems and methods to measure quantum gate fidelity through swap spectroscopy. In particular, aspects of the present disclosure are directed to the derivation and use of a physical model that models non-Markovian quantum dynamics of interactions between one or more qubits of a quantum gate and one or more two-level-system (TLS) defects during operation of the quantum gate.
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公开(公告)号：US11809957B2
公开(公告)日：2023-11-07
申请号：US16981606
申请日：2019-01-31
Applicant: Google LLC
Inventor： Yuezhen Niu , Vadim Smelyanskiy , Sergio Boixo Castrillo
Abstract: Methods, systems and apparatus for implementing a quantum gate on a quantum system comprising a second qubit coupled to a first qubit and a third qubit. In one aspect, a method includes evolving a state of the quantum system for a predetermined time, wherein during evolving: the ground and first excited state of the second qubit are separated by a first energy gap ω; the first and second excited state of the second qubit are separated by a second energy gap equal to a first multiple of ω minus qubit anharmoniticity−; the ground and first excited state of the first qubit and third qubit are separated by a third energy gap equal to ω−; and the first and second excited state of the first qubit and third qubit are separated by a fourth energy gap equal to the first multiple of the ω minus a second multiple of .
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公开(公告)号：US20220383180A1
公开(公告)日：2022-12-01
申请号：US17623399
申请日：2019-10-23
Applicant: Google LLC
Inventor： Sergio Boixo Castrillo , Craig Gidney , Adam Zalcman
IPC: G06N10/70
Abstract: Methods, systems and apparatus for estimating quantum processor performance. In one aspect, a method includes defining a benchmarking circuit configured to operate on an array of qubits, wherein the benchmarking circuit comprises one or more cycles of quantum gates, each cycle comprising a respective layer of randomly sampled single-qubit gates and a layer of multiple instances of a same multi-qubit gate; partitioning the defined benchmarking circuit into two or more sub-circuits, comprising: defining one or more boundaries between qubits in the array of qubits, removing instances of the multi-qubit gate that cross the defined one or more boundaries to create the two or more sub-circuits; performing a benchmarking process using the partitioned benchmarking circuit to estimate a respective circuit fidelity of each of the sub-circuits; and multiplying the estimated circuit fidelities of each of the sub-circuits to obtain an estimate of the fidelity of the quantum processor.
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公开(公告)号：US20220027773A1
公开(公告)日：2022-01-27
申请号：US17433445
申请日：2019-03-05
Applicant: Google LLC
Inventor： Vadim Smelyanskiy , Andre Petukhov , Rami Barends , Sergio Boixo Castrillo , Yu Chen
IPC: G06N10/00
Abstract: Methods, systems and apparatus for generating plunge schedules for implementing iSWAP quantum logic gates between a first qubit and a second qubit. In one aspect, a plunge schedule that defines a trajectory of a detuning between a frequency of the first qubit and a frequency of the second qubit includes, during a first stage, non-adiabatically driving detuning between the frequency of the first qubit and the frequency of the second qubit through a first avoided crossing in a leakage channel, during a second stage, driving detuning between the frequency of the first qubit and the frequency of the second qubit through a second avoided crossing in a swap channel. during a third stage, allowing the first qubit and the second qubit to freely evolve and interact, during a fourth stage, implementing the second stage in reverse order, and during a fifth stage, implementing the first stage in reverse order.
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公开(公告)号：US12299533B2
公开(公告)日：2025-05-13
申请号：US18080614
申请日：2022-12-13
Applicant: Google LLC
Inventor： Sergio Boixo Castrillo , Vadim Smelyanskiy
IPC: G06N10/20 , G06F7/544 , G06F30/3308 , G06N10/80
Abstract: Methods, systems and apparatus for simulating quantum circuits including multiple quantum logic gates. In one aspect, a method includes the actions of representing the multiple quantum logic gates as functions of one or more classical Boolean variables that define a undirected graphical model with each classical Boolean variable representing a vertex in the model and each function of respective classical Boolean variables representing a clique between vertices corresponding to the respective classical Boolean variables; representing the probability of obtaining a particular output bit string from the quantum circuit as a first sum of products of the functions; and calculating the probability of obtaining the particular output bit string from the quantum circuit by directly evaluating the sum of products of the functions. The calculated partition function is used to (i) calibrate, (ii) validate, or (iii) benchmark quantum computing hardware implementing a quantum circuit.
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Patent Agency Ranking
公开(公告)号：US12067457B2
公开(公告)日：2024-08-20
申请号：US16981075
申请日：2019-01-31
Applicant: Google LLC
Inventor： Vadim Smelyanskiy , Andre Petukhov , Rami Barends , Sergio Boixo Castrillo
IPC: H03K19/195 , G06N10/00 , G06N10/20 , G06N10/60
Abstract: Methods, systems and apparatus for implementing iSWAP quantum logic gates between a first qubit and a second qubit. In one aspect, a method includes implementing a cascade schedule that defines a trajectory of a detuning between a frequency of the first qubit and a frequency of the second qubit. Implementing the cascade schedule includes: during a first stage, adiabatically driving detuning between the frequency of the first qubit and the frequency of the second qubit through a first avoided crossing in a leakage channel; during a second stage, driving detuning between the frequency of the first qubit and the frequency of the second qubit through a second avoided crossing in a swap channel; during a third stage, evolving the first qubit and second qubit; during a fourth stage, implementing the second stage in reverse order; and during a fifth stage, implementing the first stage in reverse order.
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公开(公告)号：US20220374750A1
公开(公告)日：2022-11-24
申请号：US17623385
申请日：2019-10-25
Applicant: Google LLC
Inventor： Vadim Smelyanskiy , Alexander Korotkov , Sergio Boixo Castrillo
Abstract: Methods, systems and apparatus for estimating the fidelity of a quantum computing system. In one aspect, a method includes defining one or more random quantum circuits, wherein a noisy experimental implementation of each random quantum circuit is approximated by a depolarizing channel with respective polarization parameter; generating, for each defined random quantum circuit and by the quantum computing system, a set of experimental data, wherein data items in the set of experimental data comprise measured bit strings corresponding to experimental implementations of the random quantum circuit; determining, for each of the one or more random quantum circuits, an estimate of the respective polarization parameter, comprising maximizing a log-likelihood of the polarization parameter conditioned on the respective set of experimental data using series inversion; and determining an estimate of the fidelity of the quantum computing system based on the determined estimates of respective polarization parameters.
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公开(公告)号：US20220230087A1
公开(公告)日：2022-07-21
申请号：US17623128
申请日：2019-10-30
Applicant: Google LLC
Inventor： Sergio Boixo Castrillo , Vadim Smelyanskiy , Hartmut Neven , Alexander Korotkov
Abstract: Methods, systems and apparatus for estimating the fidelity of quantum logic gates. In one aspect, a method includes defining multiple sets of random quantum circuits; for each set of random quantum circuits: selecting an observable for each element in the set of random quantum circuits, wherein each selected observable corresponds to a respective element of the set of random quantum circuits and is dependent on the element to which it corresponds; estimating a value of a polarization parameter for the set of random quantum circuits, comprising performing a least mean squares minimization based on multiple expectation values, wherein each expectation value comprises an expectation value of a respective selected observable with respect to an output of an experimental implementation of a random quantum circuit corresponding to the respective selected observable; and processing the estimated polarization parameter values to obtain an estimate of the fidelity of the n-qubit quantum logic gate.
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公开(公告)号：US20220012622A1
公开(公告)日：2022-01-13
申请号：US17339276
申请日：2021-06-04
Applicant: Google LLC
Inventor： Yuezhen Niu , Hartmut Neven , Vadim Smelyanskiy , Sergio Boixo Castrillo
Abstract: Methods, systems, and apparatus for implementing a unitary quantum gate on one or more qubits. In one aspect, a method includes the actions designing a control pulse for the unitary quantum gate, comprising: defining a universal quantum control cost function, wherein the control cost function comprises a qubit leakage penalty term representing i) coherent qubit leakage, and ii) incoherent qubit leakage across all frequency components during a time dependent Hamiltonian evolution that realizes the unitary quantum gate; adjusting parameters of the time dependent Hamiltonian evolution to vary a control cost according to the control cost function such that leakage errors are reduced; generating the control pulse using the adjusted parameters; and applying the control pulse to the one or more qubits to implement the unitary quantum gate.
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公开(公告)号：US12229635B2
公开(公告)日：2025-02-18
申请号：US17574192
申请日：2022-01-12
Applicant: Google LLC
Inventor： John Martinis , Nan Ding , Ryan Babbush , Sergei V. Isakov , Hartmut Neven , Vadim Smelyanskiy , Sergio Boixo Castrillo
IPC: G06N10/00
Abstract: Methods and apparatus for estimating the fidelity of quantum hardware. In one aspect, a method includes accessing a set of quantum gates; sampling a subset of quantum gates from the set of quantum gates, wherein the subset of quantum gates defines a quantum circuit; applying the quantum circuit to a quantum system and performing measurements on the quantum system to determine output information of the quantum system; calculating output information of the quantum system based on application of the quantum circuit to the quantum system; and estimating a fidelity of the quantum circuit based on the determined output information and the calculated output information of the quantum system.
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