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    Advancement mechanism for cartridge-based devices
    1.
    发明授权
    Advancement mechanism for cartridge-based devices 有权
    基于盒式设备的推进机制

    公开(公告)号：US09517027B2

    公开(公告)日：2016-12-13

    申请号：US12892324

    申请日：2010-09-28

    申请人： Gil Kan ,  Brian M. Collins ,  Gregory Lamps

    发明人： Gil Kan ,  Brian M. Collins ,  Gregory Lamps

    IPC分类号： A61B5/00 ,  A61B5/151 ,  A61B5/15

    CPC分类号： A61B5/15182 ,  A61B5/1411 ,  A61B5/150022 ,  A61B5/150175 ,  A61B5/150259 ,  A61B5/150412 ,  A61B5/150702 ,  A61B5/15113 ,  A61B5/15117 ,  A61B5/15126 ,  A61B5/1513 ,  A61B5/15132 ,  A61B5/15146 ,  A61B5/15148 ,  A61B5/15151 ,  A61B5/15161 ,  A61B50/3001

    摘要： An advancement mechanism of a lancing device operates to sequentially advance lancets in a cartridge. The advancement mechanism includes a rotary drive gear assembly with a first gear and a second gear that co-rotate in a first angular direction by operation of an inter-gear unidirectional drive mechanism such as a ratcheting mechanism. A second-gear unidirectional lock mechanism, such as a ratcheting mechanism, locks the second drive gear from co-rotating with the first drive gear in a second opposite angular direction without impeding rotation in the first direction. The second gear directly or indirectly rotationally drives a pinion gear, which rotationally drives a cartridge gear to advance the lancets in indexed increments for use. The first drive gear is rotated in the first and second directions by a rack gear of a translating operating handle. In addition, a rotary-gear cap-displacement mechanism and a rotary-gear charging/actuation mechanism are provided in other embodiments.

    摘要翻译： 穿刺装置的推进机构操作以顺序地推进筒中的刺血针。 前进机构包括具有第一齿轮和第二齿轮的旋转驱动齿轮组件，其通过诸如棘轮机构的齿轮间单向驱动机构的操作沿第一角度方向共同旋转。 诸如棘轮机构的二档单向锁定机构锁定第二驱动齿轮与第一驱动齿轮在第二相反的角度方向上与第一驱动齿轮共旋转而不阻碍第一方向的旋转。 第二齿轮直接或间接地旋转地驱动小齿轮，该小齿轮旋转地驱动筒齿轮，以按指数的增量推进刺血针以供使用。 第一驱动齿轮通过平移操作手柄的齿条在第一和第二方向上旋转。 此外，在其他实施例中提供了旋转齿轮盖移位机构和旋转齿轮充气/致动机构。

    Device and method for increased fault coverage using scan insertion techniques around synchronous memory
    4.
    发明授权
    Device and method for increased fault coverage using scan insertion techniques around synchronous memory 有权
    使用围绕同步存储器的扫描插入技术增加故障覆盖的设备和方法

    公开(公告)号：US06587996B1

    公开(公告)日：2003-07-01

    申请号：US09593600

    申请日：2000-06-12

    申请人： Richard D. Reohr, Jr. ,  Brian M. Collins

    发明人： Richard D. Reohr, Jr. ,  Brian M. Collins

    IPC分类号： G06F1750

    CPC分类号： G11C29/48 ,  G01R31/318533 ,  G01R31/318558 ,  G11C11/41 ,  G11C2029/0401 ,  G11C2029/3202

    摘要： A device and method to test a circuit in a chip that has memory embedded in the chip using a scan chain. This device and method generates a known signal simultaneously to a bypass circuit and the memory onboard the chip. The bypass circuit uses a series of exclusive OR gates, a flip-flop, and a multiplexer to receive the known signal. The exclusive OR gates reduce the number of signals input so that they match the number of signals output by memory. A flip-flop is used to store the data received from the exclusive OR gates and transfer it to a multiplexer. The multiplexer receives data from memory and the flip-flop and selects which data to pass on in the circuit. When a scan test is being run on the circuit the multiplexer passes on only the data from the flip-flop. When a scan test is not being run the multiplexer only passes on the data from memory. This device and method allows for circuits to be tested using a scan chain that could not otherwise be tested due to the presence of memory embedded in the chip.

    摘要翻译： 一种使用扫描链测试芯片中具有嵌入在芯片中的存储器的电路的装置和方法。 该装置和方法同时产生已知信号到旁路电路和芯片上的存储器。 旁路电路使用一系列异或门，触发器和多路复用器来接收已知信号。 异或门减少输入信号的数量，使其与存储器输出的信号数相匹配。 触发器用于存储从异或门接收到的数据并将其传送到多路复用器。 多路复用器从存储器和触发器接收数据，并选择在电路中传递哪些数据。 当在电路上运行扫描测试时，多路复用器仅传递来自触发器的数据。 当扫描测试没有运行时，多路复用器仅传递来自存储器的数据。 该器件和方法允许使用扫描链测试电路，由于存在嵌入在芯片中的存储器，否则无法进行测试。

    NAVIGATING AMONG HIGHER-LEVEL AND LOWER-LEVEL WINDOWS ON A COMPUTING DEVICE
    6.
    发明申请
    NAVIGATING AMONG HIGHER-LEVEL AND LOWER-LEVEL WINDOWS ON A COMPUTING DEVICE 审中-公开
    在计算机设备上的高级和低级窗口导航

    公开(公告)号：US20120174030A1

    公开(公告)日：2012-07-05

    申请号：US12980384

    申请日：2010-12-29

    申请人： Nirmalya Barat ,  Brian M. Collins ,  Ansuman Tapan Satpathy

    发明人： Nirmalya Barat ,  Brian M. Collins ,  Ansuman Tapan Satpathy

    IPC分类号： G06F3/048

    CPC分类号： G06F3/0481 ,  G06F9/451

    摘要： Disclosed are methods for consistent navigation among higher-level and lower-level windows on a device's display screen. A user can consistently navigate from one higher-level window to another and use the same navigation tools to navigate among the lower-level windows (if any) within a higher-level window. Some embodiments present a set of small “overviews” to the user. Each overview corresponds to one of the higher-level windows. In addition to the set of overviews, a larger “preview” can be shown of the window with focus. If the window with focus contains lower-level windows, then the preview can include “snapshots” of those lower-level windows. In some embodiments, a “title bar” provides more information about the window with focus, such as the title of that window. When a lower-level window is currently active within the higher-level window with focus, the title bar can show information about that active lower-level window.

    摘要翻译： 公开的是用于在设备的显示屏幕上的上级和下级窗口之间的一致导航的方法。 用户可以一致地从一个更高级别的窗口导航到另一个窗口，并使用相同的导航工具在较高级窗口中的下级窗口（如果有的话）中导航。 一些实施例向用户呈现一组小的“概述”。 每个概览对应于其中一个较高级别的窗口。 除了一套概述之外，还可以通过焦点来显示更大的“预览”窗口。 如果具有焦点的窗口包含较低级别的窗口，则预览可以包括那些较低级窗口的“快照”。 在一些实施例中，“标题栏”提供关于具有焦点的窗口的更多信息，例如该窗口的标题。 当较低级别的窗口当前在具有焦点的较高级别窗口中处于活动状态时，标题栏可以显示有关该活动下级窗口的信息。

    Controller which determines presence of memory in a node of a data network
    7.
    发明授权
    Controller which determines presence of memory in a node of a data network 有权
    确定数据网络节点中的存储器的存在的控制器

    公开(公告)号：US06842840B1

    公开(公告)日：2005-01-11

    申请号：US09793751

    申请日：2001-02-27

    申请人： Richard D. Reohr, Jr. ,  Brian M. Collins

    发明人： Richard D. Reohr, Jr. ,  Brian M. Collins

    IPC分类号： G06F12/00 ,  G06F13/16 ,  G11C8/00 ,  H04L12/56

    CPC分类号： G06F13/1694 ,  H04L49/252 ,  H04L49/35 ,  H04L49/506

    摘要： A system for determining whether a memory is connected to a controller in a node of a data network. In order to utilize non-volatile memory elsewhere in the system, it is possible to eliminate the EEPROM which is normally connected to the controller. In order to indicate that the EEPROM is deliberately missing, a pull-up resistor connected to a voltage source is connected to the chip select signal line which normally runs between the controller and the EEPROM. If a high signal is received, the controller knows that the EEPROM is deliberately missing and that non-volatile memory will be provided elsewhere in the system.

    摘要翻译： 一种用于确定存储器是否连接到数据网络的节点中的控制器的系统。 为了在系统中的其他地方使用非易失性存储器，可以消除正常连接到控制器的EEPROM。 为了表明EEPROM故意丢失，连接到电压源的上拉电阻连接到通常在控制器和EEPROM之间运行的芯片选择信号线。 如果接收到高信号，则控制器知道EEPROM故意丢失，并且非易失性存储器将在系统的其他地方提供。

    Apparatus and method for a channel adapter non-contiguous translation protection table
    8.
    发明授权
    Apparatus and method for a channel adapter non-contiguous translation protection table 有权
    用于通道适配器的非连续翻译保护表的装置和方法

    公开(公告)号：US06718453B2

    公开(公告)日：2004-04-06

    申请号：US09816078

    申请日：2001-03-26

    申请人： Brian M. Collins ,  Dick Reohr

    发明人： Brian M. Collins ,  Dick Reohr

    IPC分类号： G06F1210

    CPC分类号： G06F12/145 ,  G06F12/1081

    摘要： A method and apparatus for non-contiguous translation protection table that includes one or more first registers, two or more second registers, an address translator, and a detector. Each first register contains a value denoting a size of each of two or more blocks of memory. Each second register contains a value denoting the starting physical address of an associated one of the two or more blocks of memory. The address translator receives a virtual address and translates the virtual address to a physical address of one of the two or more blocks of memory. The detector detects whether the received virtual address is outside of the range of the two or more blocks of memory. The blocks of memory may be translation protection tables that reside in physically non-contiguous memory locations.

    摘要翻译： 一种用于非连续翻译保护表的方法和装置，包括一个或多个第一寄存器，两个或多个第二寄存器，地址转换器和检测器。 每个第一个寄存器包含一个表示两个或更多块存储器的大小的值。 每个第二寄存器包含表示两个或更多个存储器块中相关联的一个的起始物理地址的值。 地址转换器接收虚拟地址并将虚拟地址转换为两个或更多个存储器块之一的物理地址。 检测器检测接收到的虚拟地址是否在两个或更多块存储器的范围之外。 存储器块可以是位于物理上不连续的存储器位置的转换保护表。

    Device and method to test on-chip memory in a production environment
    10.
    发明授权
    Device and method to test on-chip memory in a production environment 失效
    在生产环境中测试片上存储器的器件和方法

    公开(公告)号：US06671837B1

    公开(公告)日：2003-12-30

    申请号：US09588005

    申请日：2000-06-06

    申请人： Richard D. Reohr, Jr. ,  Brian M. Collins

    发明人： Richard D. Reohr, Jr. ,  Brian M. Collins

    IPC分类号： G11C2900

    CPC分类号： G11C29/1201 ,  G11C29/16 ,  G11C2207/104

    摘要： A device and method to test memory embedded in a chip in which the memory is not directly accessible from a tester external to the chip. The device and method uses a state machine embedded in control circuitry of the chip to execute software to test the memory embedded on the chip. The software in turn employs a row and column address generator connected to the state machine to access each memory location in the memory embedded in the chip. A data generator is also used by the software to generate and write data to memory locations specified by the row and column address generator. Several multiplexers are used to accept data from the data generator and pass the data to the memory embedded in the chip. These multiplexers act to enable reads and writes to memory when a memory test is performed or to enable normal reads and writes to memory when normal operations of the chip are executed. A data comparator is used to determine if the memory is working properly.

    摘要翻译： 一种用于测试嵌入在芯片中的存储器的设备和方法，其中存储器不能从芯片外部的测试仪直接访问。 该器件和方法使用嵌入在芯片的控制电路中的状态机来执行软件来测试嵌入在芯片上的存储器。 该软件又采用连接到状态机的行和列地址发生器来访问嵌入在芯片中的存储器中的每个存储器位置。 软件还使用数据生成器来生成和写入数据到由行和列地址生成器指定的存储单元。 几个多路复用器被用于接收来自数据发生器的数据，并将数据传送到嵌入在芯片中的存储器。 当执行存储器测试时，这些多路复用器用于使能对存储器的读取和写入，或者当执行芯片的正常操作时能够对存储器进行正常读取和写入。 数据比较器用于确定存储器是否正常工作。