Etch profile control during skip via formation

    公开(公告)号:US10109526B1

    公开(公告)日:2018-10-23

    申请号:US15609408

    申请日:2017-05-31

    Abstract: Structures for a skip via and methods of forming a skip via in an interconnect structure. A metallization level is formed that includes a dielectric layer with a top surface. An opening is formed that extends vertically from the top surface of the dielectric layer into the dielectric layer. A dielectric cap layer is deposited on a bottom surface of the opening. A fill layer is formed inside the opening and extends from the top surface of the dielectric layer to the dielectric cap layer on the bottom surface of the opening. A via opening is etched that extends vertically through the fill layer to the dielectric cap layer on the bottom surface of the opening.

Patent Agency Ranking