公开(公告)号：US10163697B2

公开(公告)日：2018-12-25

申请号：US15478385

申请日：2017-04-04

申请人： GlobalFoundries Inc.

发明人： Felix P. Anderson ,  Edward C. Cooney, III ,  Michael S. Dusablon ,  David C. Mosher

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02

摘要： Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.

公开(公告)号：US09673091B2

公开(公告)日：2017-06-06

申请号：US14749817

申请日：2015-06-25

申请人： GLOBALFOUNDRIES INC.

发明人： Felix P. Anderson ,  Edward C. Cooney, III ,  Michael S. Dusablon ,  David C. Mosher

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/02164 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76886 ,  H01L23/53238

摘要： Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.

公开(公告)号：US20170207121A1

公开(公告)日：2017-07-20

申请号：US15478385

申请日：2017-04-04

申请人： GlobalFoundries Inc.

发明人： Felix P. Anderson ,  Edward C. Cooney, III ,  Michael S. Dusablon ,  David C. Mosher

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/02164 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76886 ,  H01L23/53238

摘要： Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.