公开(公告)号：US11864316B2

公开(公告)日：2024-01-02

申请号：US17630630

申请日：2021-07-16

Applicant: Fujikura Ltd.

Inventor： Naoki Oyaizu ,  Yusuke Fujita ,  Toshiaki Inoue ,  Shinya Kashima

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H05K2201/0305 ,  H05K2201/09481 ,  H05K2201/09545 ,  H05K2201/09563

Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, and a plurality of filled vias. The first insulating layer has a first surface and a second surface positioned on a side opposite to the first surface. The first conductor layer is formed on the first surface of the first insulating layer. The plurality of filled vias are formed inside the first insulating layer. The plurality of filled vias each have a structure in which a via hole penetrating the first insulating layer is filled with a metal. The first conductor layer includes a pad. The pad overlaps the plurality of filled vias in a plan view from a thickness direction of the first insulating layer and is connected to the plurality of filled vias.

公开(公告)号：US20220361330A1

公开(公告)日：2022-11-10

申请号：US17630630

申请日：2021-07-16

Applicant: Fujikura Ltd.

Inventor： Naoki Oyaizu ,  Yusuke Fujita ,  Toshiaki Inoue ,  Shinya Kashima

IPC: H05K1/11

Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, and a plurality of filled vias. The first insulating layer has a first surface and a second surface positioned on a side opposite to the first surface. The first conductor layer is formed on the first surface of the first insulating layer. The plurality of filled vias are formed inside the first insulating layer. The plurality of filled vias each have a structure in which a via hole penetrating the first insulating layer is filled with a metal. The first conductor layer includes a pad. The pad overlaps the plurality of filled vias in a plan view from a thickness direction of the first insulating layer and is connected to the plurality of filled vias.