公开(公告)号：US20210181957A1

公开(公告)日：2021-06-17

申请号：US16712253

申请日：2019-12-12

Applicant: Facebook, Inc.

Inventor： Abdulkadir Utku Diril ,  Olivia Wu ,  Krishnakumar Narayanan Nair ,  Aravind Kalaiah ,  Anup Ramesh Kadkol ,  Pankaj Kansal

IPC: G06F3/06 ,  G06N3/02

Abstract: A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.

公开(公告)号：US20210182196A1

公开(公告)日：2021-06-17

申请号：US16717998

申请日：2019-12-17

Applicant: Facebook, Inc.

Inventor： Olivia Wu ,  Abdulkadir Utku Diril ,  Krishnakumar Narayanan Nair ,  Aravind Kalaiah ,  Anup Ramesh Kadkol ,  Pankaj Kansal

IPC: G06F12/0813 ,  G06F13/16 ,  G06N3/02

Abstract: A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. Each request processing unit includes a plurality of decomposition units and a crossbar switch, the crossbar switch communicatively connecting each of the plurality of decomposition units to each of the plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access the plurality of memory units using a dynamically programmable distribution scheme.

公开(公告)号：US20210326051A1

公开(公告)日：2021-10-21

申请号：US17307828

申请日：2021-05-04

Applicant: Facebook, Inc.

Inventor： Abdulkadir Utku Diril ,  Olivia Wu ,  Krishnakumar Narayanan Nair ,  Aravind Kalaiah ,  Anup Ramesh Kadkol ,  Pankaj Kansal

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/80 ,  G06N3/02

Abstract: A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.

公开(公告)号：US11054998B1

公开(公告)日：2021-07-06

申请号：US16712253

申请日：2019-12-12

Applicant: Facebook, Inc.

Inventor： Abdulkadir Utku Diril ,  Olivia Wu ,  Krishnakumar Narayanan Nair ,  Aravind Kalaiah ,  Anup Ramesh Kadkol ,  Pankaj Kansal

IPC: G06F12/00 ,  G06F3/06 ,  G06N3/02 ,  G06F13/16 ,  G06F15/80

Abstract: A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.

公开(公告)号：US20210165691A1

公开(公告)日：2021-06-03

申请号：US16701019

申请日：2019-12-02

Applicant: Facebook, Inc.

Inventor： Abdulkadir Utku Diril ,  Olivia Wu ,  Krishnakumar Narayanan Nair ,  Anup Ramesh Kadkol ,  Aravind Kalaiah ,  Pankaj Kansal

IPC: G06F9/50 ,  G06F9/54 ,  G06F9/445 ,  G06F9/38 ,  G06F12/02

Abstract: A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access data from the plurality of memory units using a dynamically programmable distribution scheme.