公开(公告)号：US20210326051A1

公开(公告)日：2021-10-21

申请号：US17307828

申请日：2021-05-04

Applicant: Facebook, Inc.

Inventor： Abdulkadir Utku Diril ,  Olivia Wu ,  Krishnakumar Narayanan Nair ,  Aravind Kalaiah ,  Anup Ramesh Kadkol ,  Pankaj Kansal

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/80 ,  G06N3/02

Abstract: A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.

公开(公告)号：US11054998B1

公开(公告)日：2021-07-06

申请号：US16712253

申请日：2019-12-12

Applicant: Facebook, Inc.

Inventor： Abdulkadir Utku Diril ,  Olivia Wu ,  Krishnakumar Narayanan Nair ,  Aravind Kalaiah ,  Anup Ramesh Kadkol ,  Pankaj Kansal

IPC: G06F12/00 ,  G06F3/06 ,  G06N3/02 ,  G06F13/16 ,  G06F15/80

Abstract: A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.

公开(公告)号：US20210165691A1

公开(公告)日：2021-06-03

申请号：US16701019

申请日：2019-12-02

Applicant: Facebook, Inc.

Inventor： Abdulkadir Utku Diril ,  Olivia Wu ,  Krishnakumar Narayanan Nair ,  Anup Ramesh Kadkol ,  Aravind Kalaiah ,  Pankaj Kansal

IPC: G06F9/50 ,  G06F9/54 ,  G06F9/445 ,  G06F9/38 ,  G06F12/02

Abstract: A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access data from the plurality of memory units using a dynamically programmable distribution scheme.

公开(公告)号：US20210181957A1

公开(公告)日：2021-06-17

申请号：US16712253

申请日：2019-12-12

Applicant: Facebook, Inc.

Inventor： Abdulkadir Utku Diril ,  Olivia Wu ,  Krishnakumar Narayanan Nair ,  Aravind Kalaiah ,  Anup Ramesh Kadkol ,  Pankaj Kansal

IPC: G06F3/06 ,  G06N3/02

Abstract: A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.

公开(公告)号：US10777251B1

公开(公告)日：2020-09-15

申请号：US16408331

申请日：2019-05-09

Applicant: Facebook, Inc.

Inventor： Ahmad Byagowi ,  Aravind Kalaiah ,  Mikhail Smelyanskiy

IPC: G11C11/24 ,  G11C11/405 ,  G11C11/404 ,  H01L27/108

Abstract: A first value is stored in a first memory cell. A first component output current, from a first electronic component, is provided based on the stored first value, wherein the first component output current is proportional to a place value represented by the first value. A second value is stored in a second memory cell. A second component output current, from a second electronic component, is provided based on the stored second value, wherein the second component output current is proportional to a place value represented by the second value. A combined current of at least the first component output current and the second component output current is detected, wherein the combined current corresponds to a sum of at least the first value and the second value.

公开(公告)号：US20210182196A1

公开(公告)日：2021-06-17

申请号：US16717998

申请日：2019-12-17

Applicant: Facebook, Inc.

Inventor： Olivia Wu ,  Abdulkadir Utku Diril ,  Krishnakumar Narayanan Nair ,  Aravind Kalaiah ,  Anup Ramesh Kadkol ,  Pankaj Kansal

IPC: G06F12/0813 ,  G06F13/16 ,  G06N3/02

Abstract: A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. Each request processing unit includes a plurality of decomposition units and a crossbar switch, the crossbar switch communicatively connecting each of the plurality of decomposition units to each of the plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access the plurality of memory units using a dynamically programmable distribution scheme.

公开(公告)号：US20210124794A1

公开(公告)日：2021-04-29

申请号：US16667791

申请日：2019-10-29

Applicant: Facebook, Inc.

Inventor： Krishnakumar Narayanan Nair ,  Olivia Wu ,  Ehsan Khish Ardestani Zadeh ,  Abdulkadir Utku Diril ,  Thomas Mark Ulrich ,  Yuchen Hao ,  Rakesh Komuravelli ,  Aravind Kalaiah

IPC: G06F17/16 ,  G06F7/544 ,  G06F17/15

Abstract: A system comprises a data input vector unit, a weight input vector unit, and a plurality of calculation units of a matrix processor unit. The data input vector unit is configured to concurrently receive elements of different rows of a first and second data matrix. The weight input vector unit is configured to receive a combined weight vector and at least in part concurrently provide obtained weight elements of a first and second weight matrix to a corresponding first and second group of calculation units. Each calculation unit of the first and second group of calculation units is configured to multiply elements from the data input vector unit with elements of the corresponding weight matrix from the weight input vector unit and sum together multiplication results of the corresponding calculation unit to at least in part determine a corresponding element in a first or second convolution result matrix.