公开(公告)号：US20190190520A1

公开(公告)日：2019-06-20

申请号：US16270323

申请日：2019-02-07

Applicant: Eta Compute, Inc.

Inventor： Chao Xu ,  Gopal Raghavan ,  Ben Wiley Melton ,  Vidura Manu Wijayasekara ,  Bryan Garnett Cope ,  David Cureton Baker ,  John Whitaker Havlicek

IPC: H03K19/003 ,  H03K19/017 ,  H03K19/177

CPC classification number: H03K19/003 ,  H03K19/01707 ,  H03K19/177

Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.

公开(公告)号：US10951212B2

公开(公告)日：2021-03-16

申请号：US16270323

申请日：2019-02-07

Applicant: Eta Compute, Inc.

Inventor： Chao Xu ,  Gopal Raghavan ,  Ben Wiley Melton ,  Vidura Manu Wijayasekara ,  Bryan Garnett Cope ,  David Cureton Baker ,  John Whitaker Havlicek

IPC: H03K19/003 ,  H03K19/177 ,  H03K19/017

Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.

公开(公告)号：US10205453B2

公开(公告)日：2019-02-12

申请号：US15948733

申请日：2018-04-09

Applicant: Eta Compute, Inc.

Inventor： Chao Xu ,  Gopal Raghavan ,  Ben Wiley Melton ,  Vidura Manu Wijayasekara ,  Bryan Garnett Cope ,  David Cureton Baker ,  John Whitaker Havlicek

IPC: H03K19/003 ,  H03K19/177

Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.

公开(公告)号：US20180294810A1

公开(公告)日：2018-10-11

申请号：US15948733

申请日：2018-04-09

Applicant: Eta Compute, Inc.

Inventor： Chao Xu ,  Gopal Raghavan ,  Ben Wiley Melton ,  Vidura Manu Wijayasekara ,  Bryan Garnett Cope ,  David Cureton Baker ,  John Whitaker Havlicek

IPC: H03K19/003 ,  H03K19/177

CPC classification number: H03K19/003 ,  H03K19/01707 ,  H03K19/177

Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.