Invention Application
- Patent Title: SELF-TIMED PROCESSORS IMPLEMENTED WITH MULTI-RAIL NULL CONVENTION LOGIC AND UNATE GATES
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Application No.: US16270323Application Date: 2019-02-07
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Publication No.: US20190190520A1Publication Date: 2019-06-20
- Inventor: Chao Xu , Gopal Raghavan , Ben Wiley Melton , Vidura Manu Wijayasekara , Bryan Garnett Cope , David Cureton Baker , John Whitaker Havlicek
- Applicant: Eta Compute, Inc.
- Main IPC: H03K19/003
- IPC: H03K19/003 ; H03K19/017 ; H03K19/177

Abstract:
There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.
Public/Granted literature
- US10951212B2 Self-timed processors implemented with multi-rail null convention logic and unate gates Public/Granted day:2021-03-16
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