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    Signal, interference and noise power measurement
    1.
    发明授权
    Signal, interference and noise power measurement 有权
    信号，干扰和噪声功率测量

    公开(公告)号：US07822154B2

    公开(公告)日：2010-10-26

    申请号：US10236414

    申请日：2002-09-06

    申请人： Ernest C. Chen ,  Chinh Tran

    发明人： Ernest C. Chen ,  Chinh Tran

    IPC分类号： H03D1/04

    CPC分类号： H04B7/18515 ,  H04B7/1851 ,  H04B7/18526 ,  H04B17/318 ,  H04L1/20 ,  H04L1/206 ,  H04L1/208 ,  H04L27/183 ,  H04L27/227 ,  H04L27/366 ,  H04L2027/0061

    摘要： Systems and methods are presented for measuring power levels of primary and interfering signals as well as noise, particularly for satellite transmitted signals. A typical method comprises the steps of receiving a signal comprising a primary signal, an interference signal and noise, demodulating the primary signal to remove a carrier frequency, decoding the primary signal to obtain symbols, estimating a power level of the primary signal based upon the demodulated and decoded primary signal. Additionally, an ideal primary signal can be generated from the carrier power and frequency and the symbols and subtracted from the received signal to produce the noise and interference signal. The noise and interference power is then estimated from the noise and interference signal.

    摘要翻译： 提出了系统和方法，用于测量主要和干扰信号的功率水平以及噪声，特别是卫星发射信号的噪声。 典型的方法包括以下步骤：接收包括主信号，干扰信号和噪声的信号，解调主信号以去除载波频率，解码主信号以获得符号，基于该信号估计主信号的功率电平 解调和解码的主信号。 此外，理想的主信号可以从载波功率和频率以及符号生成，并从接收信号中减去产生噪声和干扰信号。 然后从噪声和干扰信号估计噪声和干扰功率。

    Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion
    3.
    发明申请
    Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion 有权
    使用地址索引值的微处理器指令能够以循环方式访问虚拟缓冲区

    公开(公告)号：US20060075208A1

    公开(公告)日：2006-04-06

    申请号：US10956498

    申请日：2004-10-01

    申请人： Darren Jones ,  Ryan Kinter ,  Radhika Thekkath ,  Chinh Tran

    发明人： Darren Jones ,  Ryan Kinter ,  Radhika Thekkath ,  Chinh Tran

    IPC分类号： G06F12/08

    CPC分类号： G06F9/3001 ,  G06F9/30181 ,  G06F9/3552

    摘要： A modular subtraction instruction for execution on a microprocessor having at least one register. The instruction includes opcode bits for designating the instruction and operand bits for designating at least one register storing an offset index, a decrement value, and an address index. When the modular subtraction instruction is executed on the microprocessor, the address index is modified by the decrement value if the address index is not zero and is modified by the offset index if the address index is zero. For example, the address index is repeatedly decremented using the decrement value until it reaches zero, and then the address index is reset back to the offset index. The operand bits may include multiple fields identifying multiple registers selected from the general purpose registers of the microprocessor. The modular subtraction instruction enables access to a buffer in memory in circular fashion by virtue of its operation.

    摘要翻译： 一种用于在具有至少一个寄存器的微处理器上执行的模块化减法指令。 该指令包括用于指定指令的操作码位和用于指定存储偏移索引，递减值和地址索引的至少一个寄存器的操作数位。 当在微处理器上执行模块化减法指令时，如果地址索引不为零，则地址索引将通过递减值进行修改，如果地址索引为零，则由偏移索引进行修改。 例如，地址索引使用递减值重复递减，直到它达到零，然后将地址索引重置回到偏移索引。 操作数位可以包括标识从微处理器的通用寄存器中选择的多个寄存器的多个字段。 模块化减法指令通过其操作使得能够以循环方式访问存储器中的缓冲器。

    Processor core and multiplier that support both vector and single value multiplication
    10.
    发明申请
    Processor core and multiplier that support both vector and single value multiplication 有权
    处理器核心和乘数，支持向量和单值乘法

    公开(公告)号：US20060253520A1

    公开(公告)日：2006-11-09

    申请号：US11121945

    申请日：2005-05-05

    申请人： Chinh Tran

    发明人： Chinh Tran

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5318 ,  G06F2207/3828

    摘要： The present invention provides processing systems, apparatuses, and methods that support both general processing processor (GPP) and digital signal processor (DSP) features, such as vector and single value multiplication. In an embodiment, fractional arithmetic, integer arithmetic, saturation, and single instruction multiple data (SIMD) operations such as vector multiply, multiply accumulate, dot-product accumulate, and multiply-subtract accumulate are supported. In an embodiment, the process core and/or multiplier multiplies vector values or single values by creating partial products for each desired product. These partial products are added to produce intermediate results, which are combined in different ways to support various GPP and DSP operations.

    摘要翻译： 本发明提供了支持通用处理器（GPP）和数字信号处理器（DSP）特征的处理系统，装置和方法，例如向量和单值乘法。 在一个实施例中，支持分数算术，整数算术，饱和度和单指令多数据（SIMD）操作，例如向量乘法，乘法累加，点乘积累加和乘法乘法累加。 在一个实施例中，过程核心和/或乘数通过为每个期望的产品创建部分积来乘以向量值或单个值。 这些部分产品被添加以产生中间结果，其以不同的方式组合以支持各种GPP和DSP操作。