公开(公告)号：US06971103B2

公开(公告)日：2005-11-29

申请号：US10404175

申请日：2003-04-01

申请人： Erdem Hokenek ,  Mayan Moudgill ,  Sean M. Dorward

发明人： Erdem Hokenek ,  Mayan Moudgill ,  Sean M. Dorward

IPC分类号： G06F20060101 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/163

CPC分类号： G06F9/4812 ,  G06F9/30101 ,  G06F9/3851

摘要： A multithreaded processor includes an interrupt controller for processing a cross-thread interrupt directed from a requesting thread to a destination thread. The interrupt controller in an illustrative embodiment receives a request for delivery of the cross-thread interrupt to the destination thread, determines whether the destination thread of the cross-thread interrupt is enabled for receipt of cross-thread interrupts, and utilizes a thread identifier to control delivery of the cross-thread interrupt to the destination thread if the destination thread is enabled for receipt of cross-thread interrupts. The requesting thread requests delivery of the cross-thread interrupt to the destination thread by setting a corresponding interrupt pending bit in a flag register of the multithreaded processor. The destination thread is enabled for receipt of cross-thread interrupts if a corresponding enable bit is set in an enable register of the multithreaded processor. The flag and enable registers may be implemented within the interrupt controller.

摘要翻译： 多线程处理器包括用于处理从请求线程到目的线程的交叉线程中断的中断控制器。 在说明性实施例中的中断控制器接收到向目的线程传递跨线程中断的请求，确定跨线程中断的目的线程是否被启用以接收跨线程中断，并且利用线程标识符 如果目标线程被启用以接收交叉线程中断，则控制跨线程中断到目标线程的传递。 请求线程通过在多线程处理器的标志寄存器中设置相应的中断等待位来请求将交叉线程中断传送到目标线程。 如果在多线程处理器的使能寄存器中设置了相应的使能位，则使能目标线程以接收跨线程中断。 标志和使能寄存器可以在中断控制器内实现。

公开(公告)号：US08959315B2

公开(公告)日：2015-02-17

申请号：US12579867

申请日：2009-10-15

申请人： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

发明人： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3893

摘要： A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

摘要翻译： 多线程处理器包括多个硬件线程单元，耦合到用于解码从其接收的指令的线程单元的指令解码器，以及用于执行解码指令的多个执行单元。 多线程处理器被配置为用于控制与相应硬件线程单元相关联的线程的指令发布序列。 在给定的处理器时钟周期中，仅允许指定的一个线程发出一个或多个指令，但是允许发出指令的指定线程根据指令发布顺序在多个时钟周期内变化。 这些指令以允许至少给定的一个线程支持多个并行指令流水线的方式流水线化。

公开(公告)号：US08892849B2

公开(公告)日：2014-11-18

申请号：US12579893

申请日：2009-10-15

申请人： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

发明人： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

IPC分类号： G06F15/76 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3893

摘要： A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

公开(公告)号：US20100122068A1

公开(公告)日：2010-05-13

申请号：US12579867

申请日：2009-10-15

申请人： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

发明人： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

IPC分类号： G06F9/30 ,  G06F15/00 ,  G06F9/46 ,  G06F1/04

CPC分类号： G06F9/3851 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3893

摘要： A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

公开(公告)号：US06912623B2

公开(公告)日：2005-06-28

申请号：US10161874

申请日：2002-06-04

申请人： Erdem Hokenek ,  C. John Glossner ,  Arthur Joseph Hoane ,  Mayan Moudgill ,  Shenghong Wang

发明人： Erdem Hokenek ,  C. John Glossner ,  Arthur Joseph Hoane ,  Mayan Moudgill ,  Shenghong Wang

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F12/0842 ,  G06F12/0864 ,  G06F12/123 ,  G06F12/126 ,  Y02D10/13

摘要： A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing an eviction process based on access request address that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array. An entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of an address in an access request associated with the cache miss event.

摘要翻译： 用于多线程处理器的高速缓存存储器包括多个设置关联线程高速缓冲存储器，其中一个或多个线程高速缓冲存储器基于访问请求地址来实现逐出过程，所述访问请求地址减少高速缓冲存储器中所需的替换策略存储器的量 。 在说明性实施例中的至少一个线程高速缓存中的给定的一个包括具有多组存储器位置的存储器阵列和用于存储标签的目录，每个对应于存储器位置之一的特定地址的至少一部分。 目录具有多个条目，每个条目存储多个标签，使得如果存储器阵列中存在n组存储器位置，则存在与每个目录条目相关联的n个标签。 该目录用于实现访问请求和存储器阵列的存储器位置之间的集合关联地址映射。 至少部分地基于与高速缓存未命中事件相关联的访问请求中的地址的至少一部分，选择存储器位置中的特定一个存储器位置中的条目以从结合高速缓存未命中事件的给定线程高速缓存中的逐出 。

公开(公告)号：US06842848B2

公开(公告)日：2005-01-11

申请号：US10269245

申请日：2002-10-11

申请人： Erdem Hokenek ,  Mayan Moudgill ,  C. John Glossner

发明人： Erdem Hokenek ,  Mayan Moudgill ,  C. John Glossner

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F9/54 ,  G07F20060101 ,  G07F9/00

CPC分类号： G06F9/3867 ,  G06F9/3851

摘要： Techniques for token triggered multithreading in a multithreaded processor are disclosed. An instruction issuance sequence for a plurality of threads of the multithreaded processor is controlled by associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions, and utilizing the stored value to control the instruction issuance sequence. For example, each of a plurality of hardware thread units of the multithreaded processor may include a corresponding local register updatable by that hardware thread unit, with the local register for a given one of the hardware thread units storing a value identifying the next thread to be permitted to issue one or more instructions after the given hardware thread unit has issued one or more instructions. A global register arrangement may also or alternatively be used. The processor may be configured so as to permit the instruction issuance sequence to correspond to an arbitrary alternating even-odd sequence of threads, without introducing blocking conditions leading to thread stalls.

摘要翻译： 公开了一种用于多线程处理器中令牌触发多线程的技术。 多线程处理器的多个线程的指令发布序列通过与每个线程相关联来控制，该至少一个寄存器存储标识下一个线程的值以允许发出一个或多个指令，并且利用存储的值 控制指令发布顺序。 例如，多线程处理器的多个硬件线程单元中的每一个可以包括可由该硬件线程单元更新的对应的本地寄存器，其中给定的一个硬件线程单元的本地寄存器存储标识下一个线程的值 允许在给定的硬件线程单元发出一个或多个指令之后发出一个或多个指令。 还可以或替代地使用全局寄存器布置。 处理器可以被配置为允许指令发布序列对应于任意交替偶数奇数序列的线程，而不引入导致线程停顿的阻塞条件。

公开(公告)号：US08918627B2

公开(公告)日：2014-12-23

申请号：US12579912

申请日：2009-10-15

申请人： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

发明人： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3893

摘要： A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

摘要翻译： 多线程处理器包括多个硬件线程单元，耦合到用于解码从其接收的指令的线程单元的指令解码器，以及用于执行解码指令的多个执行单元。 多线程处理器被配置为用于控制与相应硬件线程单元相关联的线程的指令发布序列。 在给定的处理器时钟周期中，仅允许指定的一个线程发出一个或多个指令，但是允许发出指令的指定线程根据指令发布顺序在多个时钟周期内变化。 这些指令以允许至少给定的一个线程支持多个并行指令流水线的方式流水线化。

公开(公告)号：US08762688B2

公开(公告)日：2014-06-24

申请号：US13282800

申请日：2011-10-27

申请人： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

发明人： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

IPC分类号： G06F9/00

CPC分类号： G06F9/3851 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3893

摘要： A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

公开(公告)号：US06990557B2

公开(公告)日：2006-01-24

申请号：US10161774

申请日：2002-06-04

申请人： Erdem Hokenek ,  C. John Glossner ,  Arthur Joseph Hoane ,  Mayan Moudgill ,  Shenghong Wang

发明人： Erdem Hokenek ,  C. John Glossner ,  Arthur Joseph Hoane ,  Mayan Moudgill ,  Shenghong Wang

IPC分类号： G06F12/00

CPC分类号： G06F12/0895 ,  G06F12/0842 ,  G06F12/128

摘要： A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing a thread-based eviction process that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array. An entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of a thread identifier of the given thread cache.

公开(公告)号：US06925643B2

公开(公告)日：2005-08-02

申请号：US10269247

申请日：2002-10-11

申请人： Erdem Hokenek ,  Mayan Moudgill ,  C. John Glossner

发明人： Erdem Hokenek ,  Mayan Moudgill ,  C. John Glossner

IPC分类号： G06F9/355 ,  G06F9/38 ,  G06F12/06 ,  G06F12/08 ,  G06F9/46

CPC分类号： G06F9/342 ,  G06F9/3851 ,  G06F12/06 ,  G06F12/0842 ,  G06F12/0846 ,  Y02D10/13

摘要： Techniques for thread-based memory access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select a particular portion of an associated memory to be accessed by the corresponding processor thread. In an illustrative embodiment, a first portion of the thread identifier is utilized to select one of a plurality of multiple-bank memory elements within the memory, and a second portion of the thread identifier is utilized to select one of a plurality of memory banks within the selected one of the multiple-bank memory elements. The first portion may comprise one or more most significant bits of the thread identifier, while the second portion comprises one or more least significant bits of the thread identifier. Advantageously, the invention reduces memory access times and power consumption, while preventing the stalling of any processor threads.

摘要翻译： 公开了一种由多线程处理器进行基于线程的存储器访问的技术。 多线程处理器确定与特定处理器线程相关联的线程标识符，并且利用线程标识符的至少一部分来选择要由对应的处理器线程访问的相关联的存储器的特定部分。 在说明性实施例中，线程标识符的第一部分用于选择存储器内的多个多存储体存储器元件中的一个，并且线程标识符的第二部分用于选择多个存储体内的多个存储体， 所选择的多组存储器元件之一。 第一部分可以包括线程标识符的一个或多个最高有效位，而第二部分包括线程标识符的一个或多个最低有效位。 有利地，本发明减少了存储器访问时间和功耗，同时防止任何处理器线程的停止。