公开(公告)号：US20200301671A1

公开(公告)日：2020-09-24

申请号：US16893192

申请日：2020-06-04

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Seong-Cheon PARK

IPC: G06F7/58 ,  H03K3/84 ,  H04L9/08

Abstract: Provided is an apparatus for generating a digital value, including: an identification value generator including a plurality of unit cells; and an identification value extractor outputting an identification value of a plurality of bits by using output values of the plurality of unit cells, wherein each of the plurality of unit cells includes an identification value generating element including a first upper electrode and a second upper electrode formed on the same layer, and determines the output value according to electrical connection or cut-off of the first upper electrode and the second upper electrode.

公开(公告)号：US20230188320A1

公开(公告)日：2023-06-15

申请号：US18077621

申请日：2022-12-08

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Seong-Cheon PARK ,  Hyunwoo KIM ,  Jung-Chan NA

IPC: H04L9/00 ,  H04L9/06

CPC classification number: H04L9/008 ,  H04L9/0618

Abstract: A method of integrating different homomorphic operations in homomorphic encryption is provided. The method includes receiving a homomorphic ciphertext and encryption scheme information from a ciphertext generating apparatus by using a communication interface, performing a homomorphic multiplication operation on the homomorphic ciphertext by using a homomorphic multiplication operator, analyzing the encryption scheme information to determine one operation of a re-linearization operation performed by a re-linearization operator and a key switching operation performed by a key switching operator by using a main controller, performing the determined one operation by using the re-linearization operator or the key switching operator, and performing a modulus switching operation on an operation result of the determined one operation by using a modulus switching operator.

公开(公告)号：US20240056286A1

公开(公告)日：2024-02-15

申请号：US18447113

申请日：2023-08-09

Applicant: Electronics and Telecommunications Research Institute

Inventor： Seong-Cheon PARK

IPC: H04L9/00 ,  H04L9/06

CPC classification number: H04L9/008 ,  H04L9/0618

Abstract: Disclosed is a homomorphic encryption calculating accelerator which includes a parallel processing unit performing a polynomial multiplication operation in parallel on a plurality of input data corresponding to a degree N polynomial of a homomorphic ciphertext and a combination unit generating a plurality of output data by performing the polynomial multiplication operation on an output of the parallel processing unit. The parallel processing unit includes a first parallel processing element performing the polynomial multiplication operation on first input data among the plurality of input data and a second parallel processing element performing the polynomial multiplication operation on second input data among the plurality of input data. The first parallel processing element and the second parallel processing element are arranged in parallel, and each of the first parallel processing element and the second parallel processing element has a single-path delay feedback (SDF) number theoretic transform (NTT) hardware structure.

公开(公告)号：US20160132296A1

公开(公告)日：2016-05-12

申请号：US14938772

申请日：2015-11-11

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Seong-Cheon PARK

IPC: G06F7/58 ,  H01L23/522 ,  H03K3/037 ,  H01L27/28 ,  H01L51/00 ,  H01L51/05 ,  H01L21/768

CPC classification number: G06F7/588 ,  G06F2207/58 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0558 ,  H01L2924/0002 ,  H03K3/84 ,  H04L9/0866 ,  H01L2924/00

Abstract: Provided is an apparatus for generating a digital value, including: an identification value generator including a plurality of unit cells; and an identification value extractor outputting an identification value of a plurality of bits by using output values of the plurality of unit cells, wherein each of the plurality of unit cells includes an identification value generating element including a first upper electrode and a second upper electrode formed on the same layer, and determines the output value according to electrical connection or cut-off of the first upper electrode and the second upper electrode.

Abstract translation: 提供一种用于产生数字值的装置，包括：识别值生成器，包括多个单位单元; 以及识别值提取器，其通过使用所述多个单位单元的输出值来输出多个位的识别值，其中，所述多个单位单元中的每一个都包括识别值生成元件，所述识别值生成元件包括形成的第一上部电极和第二上部电极 并且根据第一上电极和第二上电极的电连接或切断来确定输出值。

公开(公告)号：US20240089084A1

公开(公告)日：2024-03-14

申请号：US18465861

申请日：2023-09-12

Applicant: Electronics and Telecommunications Research Institute

Inventor： Seong-Cheon PARK ,  Jung-Chan NA ,  Hyunwoo KIM ,  SUYEON JANG

IPC: H04L9/00 ,  H04L9/08

CPC classification number: H04L9/008 ,  H04L9/0861

Abstract: Disclosed is an accelerator which includes a first to a K-th stage performing an NTT (Number Theoretic Transform) operation of first input data including a polynomial of a homomorphic ciphertext, the first to K-th stages being connected in series, and a first assist circuit generating a first to a K-th enable signal based on a degree of the polynomial of the first input data. Each of the first to K-th stages performs a butterfly operation of the first input data or corresponding output data of a previous stage in response to that the corresponding enable signal among the first to K-th enable signals indicates a first logical value, and bypasses the first input data or the corresponding output data of the previous stage in response to that the corresponding enable signal among the first to K-th enable signals indicates a second logical value.

公开(公告)号：US20240022393A1

公开(公告)日：2024-01-18

申请号：US18351163

申请日：2023-07-12

Applicant: Electronics and Telecommunications Research Institute

Inventor： Seong-Cheon PARK

IPC: H04L9/00

CPC classification number: H04L9/008

Abstract: Disclosed is an accelerator device, which includes a first NTT converter that performs an NTT operation on a first ciphertext of a first type to generate a first internal signal, a test polynomial generator that generates a test polynomial, a second NTT converter that performs the NTT operation on the test polynomial to generate a second internal signal, a first multiplier that performs a multiplication on the first internal signal and the second internal signal to generate a third internal signal, a first INTT converter that performs an INTT operation on the third internal signal to generate a fourth internal signal, a gadget decomposer that performs a gadget decomposition on the fourth internal signal to generate a fifth internal signal, and a third NTT converter that performs the NTT operation on the fifth internal signal to generate a sixth internal signal.