-
公开(公告)号：US08791685B2
公开(公告)日：2014-07-29
申请号：US14098989
申请日：2013-12-06
Inventor： Young Kyun Cho , Jae Ho Jung , Kwang Chun Lee
Abstract: Disclosed is a bandgap reference voltage generator insensitive to changes of process, voltage, and temperature. A bandgap reference voltage generator may detect current having characteristic of CTAT and current having characteristic of PTAT which flow in a current compensation part included in an amplification part, and provide body voltage to one of two input transistors included in the amplification part in response to ratio of the two currents when the ratio is different from the preconfigured reference value. Thus, characteristics according to changes of parameters of elements and change of offset of the amplification part due to changes of PVT may be enhanced, and a characteristic of power supply rejection ratio (PSRR) may be enhanced.
Abstract translation: 公开了对工艺，电压和温度的变化不敏感的带隙参考电压发生器。 带隙参考电压发生器可以检测具有CTAT特性的电流和具有在包括在放大部分中的电流补偿部分中流动的PTAT特性的电流，并且响应于比率而向包括在放大部分中的两个输入晶体管之一提供体电压 当该比率与预配置的参考值不同时，两个电流。 因此，可以增加由元件参数的变化引起的特性和由于PVT变化引起的放大部分偏移的变化，并且可以提高电源抑制比（PSRR）的特性。
-
Patent Agency Ranking
公开(公告)号：US08841951B2
公开(公告)日：2014-09-23
申请号：US14067487
申请日：2013-10-30
Inventor： Hui Dong Lee , Jae Ho Jung , Kwang Chun Lee
IPC: H03K3/017
CPC classification number: H03K3/017 , H03K5/1565
Abstract: Disclosed is an apparatus for controlling a duty ratio of a signal that includes a clock control unit configured to generate a plurality of control signals based on an input signal, a half-cycle generation unit configured to generate a multiplied signal by use of the input signal and a delay signal that is obtained by delaying the input signal based on a delay control voltage, and divide the multiplied signal to generate a first division signal and a second division signal that are in inverse relation to each other, a comparator unit configured to compare a pulse width of the first division signal with a pulse width of the second division signal based on the control signal provided by the clock control unit, and output a delay control signal corresponding to a result of the comparison, and a control voltage generation unit configured to output a delay control voltage.
Abstract translation: 公开了一种用于控制信号的占空比的装置，其包括被配置为基于输入信号生成多个控制信号的时钟控制单元，半周生成单元，被配置为通过使用输入信号生成相乘的信号 以及延迟信号，其通过基于延迟控制电压延迟所述输入信号而获得，并且将所述相乘的信号除以产生彼此成反比的第一除法信号和第二除法信号，所述比较器单元被配置为比较 基于由时钟控制单元提供的控制信号的具有第二分频信号的脉冲宽度的第一分频信号的脉冲宽度，并输出与比较结果相对应的延迟控制信号，以及控制电压生成单元配置 输出延迟控制电压。
-
公开(公告)号：US09014281B2
公开(公告)日：2015-04-21
申请号：US14011268
申请日：2013-08-27
Inventor： Young Kyun Cho , Sung Jun Lee , Seung Hyun Jang , Bong Hyuk Park , Jae Ho Jung , Kwang Chun Lee
CPC classification number: H04L25/4902 , H03K7/08 , H03M3/504 , H04B14/062
Abstract: A delta-sigma modulator and a transmitter apparatus including the same are disclosed. The delta-sigma modulator includes a first integrator, a second integrator, a first comparator configured to compare an output signal of the second integrator and a reference signal, and output a first comparison signal, a second comparator configured to compare the output signal of the second integrator and the reference signal, and output a second comparison signal, a first DAC configured to output the first signal corresponding to the first comparison signal and the second comparison signal, a second DAC configured to output the second signal corresponding to the first comparison signal and the second comparison signal, a delayer configured to generate a delayed signal that delays the first comparison signal and the second comparison signal by a predetermined time, and an output DAC configured to generate an output signal having a multi-level corresponding to the delayed signal.
Abstract translation: 公开了一种Δ-Σ调制器及其发射机装置。 Δ-Σ调制器包括第一积分器，第二积分器，被配置为比较第二积分器的输出信号和参考信号的第一比较器，并输出第一比较信号;第二比较器，被配置为比较第二积分器的输出信号 第二积分器和参考信号，并输出第二比较信号，第一DAC被配置为输出对应于第一比较信号和第二比较信号的第一信号;第二DAC，被配置为输出对应于第一比较信号的第二信号 和第二比较信号，延迟器，被配置为产生将第一比较信号和第二比较信号延迟预定时间的延迟信号;以及输出DAC，被配置为产生具有与延迟信号相对应的多电平的输出信号 。
-
公开(公告)号：US11290014B2
公开(公告)日：2022-03-29
申请号：US16939567
申请日：2020-07-27
Inventor： Young Kyun Cho , Tae Joong Kim , Kwang Chun Lee , Jung Nam Lee , Jae Ho Jung
Abstract: A boost direct current-to-direct current (DC-DC) converter using a delta-sigma modulator (DSM), the boost DC-DC converter may comprise a boost driving circuit outputting an output voltage to output terminals by boosting an input voltage, a resistance distribution circuit outputting a feedback voltage by distributing the output voltage of the boost driving circuit, a compensator outputting a compensated feedback voltage by compensating for the feedback voltage outputted by the resistance distribution circuit based on a reference voltage, a delta-sigma modulator outputting a digital signal by modulating the compensated feedback voltage and a duty controller outputting a duty control signal for controlling a switching duty of the boost driving circuit by receiving the output of the delta-sigma modulator.
-
公开(公告)号：US11205998B2
公开(公告)日：2021-12-21
申请号：US16788177
申请日：2020-02-11
Inventor： Sun Woo Kong , Kwang Seon Kim , Jee Hoon Park , Kwang Chun Lee , Hui Dong Lee , Seung Hyun Jang
Abstract: An amplifier may comprise first and second matching networks; first and second transistors; and a transformer including first to third inductors. Also, a gate and a source of the first transistor are connected to the first matching network, one end of the first inductor is connected to a drain of the first transistor, the other end of the first inductor is connected to a source of the second transistor, one end of the second inductor is connected to a gate of the second transistor, the other end of the second inductor is grounded, one end of the third inductor is connected to a drain of the second transistor, and the other end of the third inductor is connected to the second matching network.
-
公开(公告)号：US09083360B2
公开(公告)日：2015-07-14
申请号：US14036736
申请日：2013-09-25
Inventor： Hui Dong Lee , Kwang Chun Lee , Jae Ho Jung
CPC classification number: H03L7/095
Abstract: A lock detector and a clock generator including the same are disclosed. A lock detector includes a counter unit which counts a non-matching section of a first signal and a second signal to provide a count value, the first signal and the second signal being comparison result signals obtained by comparing a phase of a reference signal with a phase of a comparison signal, and a lock detection unit which outputs a lock detection signal based on a result of comparing the count value with the reference value. Accordingly, a lock state of the phase-locked loop can be detected rapidly and exactly.
Abstract translation: 公开了一种锁定检测器和包括该锁定检测器的时钟发生器。 锁定检测器包括对第一信号的非匹配部分进行计数的计数器单元和提供计数值的第二信号，第一信号和第二信号是通过将参考信号的相位与 比较信号的相位;以及锁定检测单元，其基于将计数值与参考值进行比较的结果来输出锁定检测信号。 因此，可以快速且精确地检测锁相环的锁定状态。
-
-
-
-
-
Search Results
6
records
(took 0.044 seconds)
