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公开(公告)号:US12131978B2
公开(公告)日:2024-10-29
申请号:US17562587
申请日:2021-12-27
Inventor: Il Gyu Choi , Seong Il Kim , Hae Cheon Kim , Youn Sub Noh , Ho Kyun Ahn , Sang Heung Lee , Jong Won Lim , Sung Jae Chang , Hyun Wook Jung
IPC: H01L23/373 , H01L33/64
CPC classification number: H01L23/3738 , H01L23/3731
Abstract: The present invention improves a heat dissipation property of a semiconductor device by transferring hexagonal boron nitride (hBN) with a two-dimensional nanostructure to the semiconductor device. A semiconductor device of the present invention includes a substrate having a first surface and a second surface, a semiconductor layer formed on the first surface of the substrate, an hBN layer formed on at least one surface of the first surface and the second surface of the substrate, and a heat sink positioned on the second surface of the substrate. A radiation rate of heat generated during driving of an element is increased to decrease a reduction in lifetime of a semiconductor device due to a temperature increase. The semiconductor device has a structure and configuration which are very effective in improving a rapid temperature increase due to heat generated by high-power semiconductor devices.
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公开(公告)号:US12166101B2
公开(公告)日:2024-12-10
申请号:US17671171
申请日:2022-02-14
Inventor: Soo Cheol Kang , Hyun Wook Jung , Seong IL Kim , Hae Cheon Kim , Youn Sub Noh , Ho Kyun Ahn , Sang Heung Lee , Jong Won Lim , Sung Jae Chang , Il Gyu Choi
IPC: H01L29/66 , H01L29/778
Abstract: A method of manufacturing a high-electron-mobility transistor device is provided. The method includes sequentially forming a transition layer and a semiconductor layer on a substrate, etching a portion of a surface of the semiconductor layer to form a barrier layer region having a certain depth and forming a barrier layer in the barrier layer region, forming a source electrode and a drain electrode on a 2-dimensional electron gas (2-DEG) layer upward exposed at a surface of the semiconductor layer, in defining the 2-DEG layer formed along an interface between the semiconductor layer and the barrier layer, forming a passivation layer on the semiconductor layer, the barrier layer, the source electrode, and the drain electrode and etching a portion of the passivation layer to upward expose the source electrode, the drain electrode, and the barrier layer, and forming a gate electrode on the upward exposed barrier layer.
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