Method, apparatus and system to generate an interrupt by monitoring an external interface
    1.
    发明授权
    Method, apparatus and system to generate an interrupt by monitoring an external interface 有权
    通过监视外部接口产生中断的方法,装置和系统

    公开(公告)号:US07386640B2

    公开(公告)日:2008-06-10

    申请号:US11025381

    申请日:2004-12-28

    IPC分类号: G06F3/00

    CPC分类号: G06F13/22 G06F13/24

    摘要: In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over a serial interface with an input/output (I/O) extender and to save a relevant status of the I/O extender in a memory. Other embodiments are also disclosed and claimed.

    摘要翻译: 在一些实施例中,呈现通过监视外部接口来产生中断的方法,装置和系统。 在这方面,引入一个中断代理程序通过串行接口与输入/输出(I / O)扩展器进行通信,并将I / O扩展器的相关状态保存在存储器中。 还公开并要求保护其他实施例。

    Method, apparatus and system to generate an interrupt by monitoring an external interface
    2.
    发明申请
    Method, apparatus and system to generate an interrupt by monitoring an external interface 有权
    通过监视外部接口产生中断的方法,装置和系统

    公开(公告)号:US20060143351A1

    公开(公告)日:2006-06-29

    申请号:US11025381

    申请日:2004-12-28

    IPC分类号: G06F13/24

    CPC分类号: G06F13/22 G06F13/24

    摘要: In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over a serial interface with an input/output (I/O) extender and to save a relevant status of the I/O extender in a memory. Other embodiments are also disclosed and claimed.

    摘要翻译: 在一些实施例中,呈现通过监视外部接口来产生中断的方法,装置和系统。 在这方面,引入一个中断代理程序通过串行接口与输入/输出(I / O)扩展器进行通信,并将I / O扩展器的相关状态保存在存储器中。 还公开并要求保护其他实施例。

    Adaptive clock enable for memory control
    3.
    发明申请
    Adaptive clock enable for memory control 审中-公开
    自适应时钟使能用于存储器控制

    公开(公告)号:US20100169700A1

    公开(公告)日:2010-07-01

    申请号:US12317869

    申请日:2008-12-29

    IPC分类号: G06F1/04

    摘要: In some embodiments a memory rank idle counter enables de-assertion of a clock enable signal of a rank of a memory for idle systems. Clock enable signal assertion is maintained when there is a lot of traffic to the memory rank. A memory rank idle time prediction counter transfers a value to the memory rank idle counter when the memory rank is idle. Other embodiments are described and claimed.

    摘要翻译: 在一些实施例中,存储器级空闲计数器使得能够取消对空闲系统的存储器的等级的时钟使能信号。 当存储器级别有大量流量时,保持时钟使能信号断言。 当存储器级空闲时,存储器级空闲时间预测计数器将值传送到存储器级空闲计数器。 描述和要求保护其他实施例。

    Mechanism for write optimization to a memory device
    4.
    发明申请
    Mechanism for write optimization to a memory device 审中-公开
    对存储器件进行写优化的机制

    公开(公告)号:US20080162799A1

    公开(公告)日:2008-07-03

    申请号:US11648483

    申请日:2006-12-28

    IPC分类号: G06F13/14

    CPC分类号: G06F13/1642

    摘要: According to one embodiment, a memory controller is disclosed. The memory controller includes a scheduler to schedule memory transactions to the DIMM and a write address queue to accumulate the write requests while the memory controller is operating in a first mode and to release the write requests to the scheduler whenever the memory controller is operating in a second mode.

    摘要翻译: 根据一个实施例,公开了一种存储器控制器。 存储器控制器包括调度器,用于在存储器控制器以第一模式操作时调度到DIMM的存储器事务和写入地址队列以累积写请求,并且每当存储器控制器在 第二模式。