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公开(公告)号：US20210190885A1
公开(公告)日：2021-06-24
申请号：US17054631
申请日：2019-05-16
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , Emile M. Hoskinson , Mark H. Volkmann , Andrew J. Berkley , George E.G. Sterling , Jed D. Whittaker
IPC: G01R33/035 , H01L39/22 , G06N10/00
Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.
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公开(公告)号：US20220123048A1
公开(公告)日：2022-04-21
申请号：US17429456
申请日：2020-02-13
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , George E.G. Sterling , Mark H. Volkmann , Colin C. Enderud
Abstract: A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.
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公开(公告)号：US20250040454A1
公开(公告)日：2025-01-30
申请号：US18790374
申请日：2024-07-31
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , George E.G. Sterling , Mark H. Volkmann , Colin C. Enderud
Abstract: A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.
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公开(公告)号：US20250038722A1
公开(公告)日：2025-01-30
申请号：US18716679
申请日：2022-12-06
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , Jed D. Whittaker , George E.G. Sterling
Abstract: In an implementation, a tunable traveling wave parametric amplifier (TWPA) includes a T-stage that includes a first DC-SQUID and a first interface inductively communicatively coupled to the first DC SQUID operable to apply a first bias to the first DC SQUID. The T-stage also includes a second DC-SQUID electrically communicatively coupled to the first DC-SQUID in series via a center node, and a second interface inductively communicatively coupled to the second DC-SQUID operable to apply a second bias to the second DC-SQUID. The TWPA also includes a shunting resonator communicatively coupled to the center node via a coupling capacitance. The shunting resonator includes a third DC-SQUID, and a third interface inductively communicatively coupled to the third DC SQUID operable to apply a third bias to the third DC SQUID. The first, second, and third biases are adjustable to improve a bandwidth of the tunable TWPA.
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公开(公告)号：US20240008372A1
公开(公告)日：2024-01-04
申请号：US18038382
申请日：2021-11-16
Applicant: D-WAVE SYSTEMS INC.
Inventor： George E.G. Sterling
Abstract: In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and a magnetic field generator operable to apply a magnetic field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a first capacitor plate having a plane, a second capacitor plate having a plane, and a dielectric interposed between the first capacitor plate and the second capacitor plate. The plane of the second capacitor plate is geometrically parallel to the plane of the first capacitor plate. In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and an electric field generator operable to apply an electric field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a pair of capacitor plates, and a dielectric interposed between the pair of plates.
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Patent Agency Ranking
公开(公告)号：US20230204691A1
公开(公告)日：2023-06-29
申请号：US18082385
申请日：2022-12-15
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , Andrew J. Berkley , Mark H. Volkmann , George E.G. Sterling , Jed D. Whittaker
IPC: G01R33/035 , G06N10/00 , H10N60/12
CPC classification number: G01R33/0354 , G06N10/00 , H10N60/12
Abstract: A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
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公开(公告)号：US20240151782A1
公开(公告)日：2024-05-09
申请号：US18517174
申请日：2023-11-22
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , Emile M. Hoskinson , Mark H. Volkmann , Andrew J. Berley , George E.G. Sterling , Jed D. Whittaker
IPC: G01R33/035 , G06N10/00 , H10N60/12
CPC classification number: G01R33/0354 , G06N10/00 , H10N60/12
Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.
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公开(公告)号：US20220011384A1
公开(公告)日：2022-01-13
申请号：US17388545
申请日：2021-07-29
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , Andrew J. Berkley , Mark H. Volkmann , George E.G. Sterling , Jed D. Whittaker
IPC: G01R33/035 , H01L39/22 , G06N10/00
Abstract: A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
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公开(公告)号：US20210057631A1
公开(公告)日：2021-02-25
申请号：US16996595
申请日：2020-08-18
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , George E.G. Sterling , Christopher B. Rich
Abstract: Addressing a superconducting flux storage device may include applying a bias current, a low-frequency flux bias, and a high-frequency flux bias in combination to cause a combined address signal level to exceed a defined address signal latching level for the superconducting flux storage device. A bias current that, in combination with a low-frequency flux bias and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ. A low-frequency flux bias that, in combination with a bias current and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ.
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公开(公告)号：US20210019646A1
公开(公告)日：2021-01-21
申请号：US16930512
申请日：2020-07-16
Applicant: D-WAVE SYSTEMS INC.
Inventor： George E.G. Sterling
Abstract: An electrical filter includes a dielectric substrate with inner and outer coils about a first region and inner and outer coils about a second region, a portion of cladding removed from wires that form the coils and coupled to electrically conductive traces on the dielectric substrate via a solder joint in a switching region. An apparatus to thermally couple a superconductive device to a metal carrier with a through-hole includes a first clamp and a vacuum pump. A composite magnetic shield for use at superconductive temperatures includes an inner layer with magnetic permeability of at least 50,000; and an outer layer with magnetic saturation field greater than 1.2 T, separated from the inner layer by an intermediate layer of dielectric. An apparatus to dissipate heat from a superconducting processor includes a metal carrier with a recess, a post that extends upwards from a base of the recess and a layer of adhesive on top of the post. Various cryogenic refrigeration systems are described.
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