公开(公告)号：US10319628B2

公开(公告)日：2019-06-11

申请号：US15715619

申请日：2017-09-26

申请人： Commissariat a l'energie atomique et aux energies alternatives

发明人： Fabien Deprat ,  Perrine Batude ,  Laurent Brunet ,  Claire Fenouillet-Beranger ,  Maud Vinet

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L21/3213

摘要： A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.