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公开(公告)号:US20180323876A1
公开(公告)日:2018-11-08
申请号:US15587449
申请日:2017-05-05
Applicant: Cisco Technology, Inc.
Inventor: Huang Ping , John Alexander Ritchie, JR.
IPC: H04B10/25 , H04B10/27 , H04B10/079
CPC classification number: H04B10/2504 , H04B10/0795 , H04B10/27
Abstract: Per-port performance optimization may be provided. First, performance data may be received corresponding to each of a plurality of ports. Then it may be determined that performance of at least one of the plurality of ports can be improved based on the received performance data corresponding to the least one of the plurality of ports. Next, in response to determining that the performance of the at least one of the plurality of ports can be improved, at least one of a plurality of components may be adjusted corresponding to the at least one of the plurality of ports to improve performance of the least one of the plurality of ports.
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公开(公告)号:US20200220622A1
公开(公告)日:2020-07-09
申请号:US16818353
申请日:2020-03-13
Applicant: Cisco Technology, Inc.
Inventor: Huang Ping , John Alexander Ritchie, JR.
IPC: H04B10/25 , H04B10/2575 , H04B10/079 , H04B10/27
Abstract: Per-port performance optimization may be provided. First, performance data may be received corresponding to each of a plurality of ports. Then it may be determined that performance of at least one of the plurality of ports can be improved based on the received performance data corresponding to the least one of the plurality of ports. Next, in response to determining that the performance of the at least one of the plurality of ports can be improved, at least one of a plurality of components may be adjusted corresponding to the at least one of the plurality of ports to improve performance of the least one of the plurality of ports.
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公开(公告)号:US20190386700A1
公开(公告)日:2019-12-19
申请号:US16008737
申请日:2018-06-14
Applicant: Cisco Technology, Inc.
Inventor: John T. Chapman , Hang Jin , John Holobinko , Yubin Chen , John Alexander Ritchie, JR. , Martin Mattingly
Abstract: Full Duplex (FDX) enhanced node deployment may be provided. First, a first device level may be provided comprising a first plurality of FDX enhanced nodes. The first plurality of FDX enhanced nodes may comprise a first FDX enhanced node and a second FDX enhanced node. The first plurality of FDX enhanced nodes may be operated in a first mode. Next, a second device level may be provided comprising a third FDX enhanced node. The second device level may be upstream from the first device level. The third FDX enhanced node may be operated in a second mode. Then an input port of the first FDX enhanced node and an input port of the second FDX enhanced node may be provided with a same type of input that is being provided to an input port of the third FDX enhanced node. The first plurality of FDX enhanced nodes may then be switched from being operated in the first mode to being operated in the second mode.
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公开(公告)号:US20200076507A1
公开(公告)日:2020-03-05
申请号:US16542977
申请日:2019-08-16
Applicant: Cisco Technology, Inc.
Inventor: John Holobinko , John Alexander Ritchie, JR.
IPC: H04B10/2575 , H04B10/516 , H04B10/079
Abstract: Dynamic power in cable access networks may be reduced. First, a peak data rate associated with a network may be determined. Then, a modulation order and an associated Radio Frequency (RF) level that will support the determined peak data rate may be determined. Next, a power value to be transmitted by a node in the network based on the determined modulation order and the associated RF level may be determined. A bias value may then be determined for the node to support the determined power value.
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公开(公告)号:US20190149235A1
公开(公告)日:2019-05-16
申请号:US16249342
申请日:2019-01-16
Applicant: Cisco Technology, Inc.
Inventor: Huang Ping , John Alexander Ritchie, JR.
IPC: H04B10/25 , H04B10/27 , H04B10/079
Abstract: Per-port performance optimization may be provided. First, performance data may be received corresponding to each of a plurality of ports. Then it may be determined that performance of at least one of the plurality of ports can be improved based on the received performance data corresponding to the least one of the plurality of ports. Next, in response to determining that the performance of the at least one of the plurality of ports can be improved, at least one of a plurality of components may be adjusted corresponding to the at least one of the plurality of ports to improve performance of the least one of the plurality of ports.
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公开(公告)号:US20190280886A1
公开(公告)日:2019-09-12
申请号:US15917430
申请日:2018-03-09
Applicant: Cisco Technology, Inc.
Inventor: John Holobinko , John Alexander Ritchie, JR. , John Skrobko , Huang Ping
Abstract: Automated intelligent node setup and configuration in a Hybrid Fiber-Coaxial (HFC) Network may be provided. First, a desired operating profile for a node connected in a Hybrid Fiber-Coaxial (HFC) network may be determined by a computing device. Next, based on the desired operating profile, a setting for at least one component in the node may be determined by the computing device. Then the at least one component in the node may be adjusted remotely by the computing device to the determined setting.
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公开(公告)号:US20190273369A1
公开(公告)日:2019-09-05
申请号:US15911382
申请日:2018-03-05
Applicant: Cisco Technology, Inc.
Inventor: William George Mahoney , John Alexander Ritchie, JR.
Abstract: A three-piece electronics enclosure may be provided. The electronics enclosure may comprise a back housing, a lid, and a center frame. The back housing may comprise back housing heat sinks on an exterior of the back housing and back housing circuitry disposed in an interior of the back housing. The lid may comprise lid heat sinks on an exterior of the lid and lid circuitry disposed in an interior of the lid. The center frame may be disposed between the back housing and the lid. The center frame may comprise a plurality of input/output (I/O) ports comprising a first I/O port and a second I/O port. At least one of the plurality of I/O ports may provide power to the back housing circuitry and the lid circuitry. The center frame may further comprise a power bypass that passes power between the first I/O port and the second I/O port.
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