公开(公告)号：US10122645B2

公开(公告)日：2018-11-06

申请号：US13708640

申请日：2012-12-07

Applicant: Cisco Technology, Inc.

Inventor： Dipankar Bhatt Acharya ,  Guglielmo Morandin ,  Rong Pan ,  Chiara Piglione ,  Hiroshi Suzuki

IPC: H04L12/863 ,  H04L12/825 ,  H04L12/935

Abstract: In one implementation, an input queue switch provides latency fairness across multiple input ports and multiple output ports. In one embodiment, each input port maintains a virtual output queue for each associate output port. The virtual output queues across multiple inputs are aggregated for each specific output port. The sum of the lengths of the virtual output queues is compared to a threshold, and based on the comparison, feedback may be generated to control the operation of the input port for subsequent packets. The feedback may instruct the input port to stop buffering or drop packets destined for the output port with the sum of the lengths of the virtual output queues associated to the specific output port that exceeds the threshold. In another embodiment, each packet has an arrival timestamp, and a virtual output queue having the oldest timestamp is selected first to dequeue.

公开(公告)号：US20180241688A1

公开(公告)日：2018-08-23

申请号：US15439144

申请日：2017-02-22

Applicant: Cisco Technology, Inc.

Inventor： John J. Williams, JR. ,  Dipankar Bhatt Acharya ,  Mohammed Ismael Tatar ,  David Delano Ward

IPC: H04L12/869 ,  H04L1/18 ,  H04L12/851

CPC classification number: H04L47/58 ,  H04L1/1835 ,  H04L45/24 ,  H04L47/30 ,  H04L49/10

Abstract: One embodiment includes multiple distribution nodes sending packets of different ordered sets of packets among multiple packet switching devices arranged in a single stage topology to reach a reordering node. The reordering node receives these packets sent over the different paths and stores them in reordering storage, such as, but not limited to, in queues for each distribution node and packet switching device combination. The reordering node sends packets stored in the reordering storage from the reordering node in original orderings. In response to determining that an aggregation quantum of packets received from the multiple distribution nodes via a particular packet switching device and stored in the reordering storage is outside a range or value, packets being communicated via the particular packet switching device to the reordering node are rate limited.

公开(公告)号：US10367751B2

公开(公告)日：2019-07-30

申请号：US15439144

申请日：2017-02-22

Applicant: Cisco Technology, Inc.

Inventor： John J. Williams, Jr. ,  Dipankar Bhatt Acharya ,  Mohammed Ismael Tatar ,  David Delano Ward

IPC: H04L12/869 ,  H04L12/851 ,  H04L1/18

Abstract: One embodiment includes multiple distribution nodes sending packets of different ordered sets of packets among multiple packet switching devices arranged in a single stage topology to reach a reordering node. The reordering node receives these packets sent over the different paths and stores them in reordering storage, such as, but not limited to, in queues for each distribution node and packet switching device combination. The reordering node sends packets stored in the reordering storage from the reordering node in original orderings. In response to determining that an aggregation quantum of packets received from the multiple distribution nodes via a particular packet switching device and stored in the reordering storage is outside a range or value, packets being communicated via the particular packet switching device to the reordering node are rate limited.

公开(公告)号：US20140161135A1

公开(公告)日：2014-06-12

申请号：US13708640

申请日：2012-12-07

Applicant: CISCO TECHNOLOGY, INC.

Inventor： Dipankar Bhatt Acharya ,  Guglielmo Morandin ,  Rong Pan ,  Chiara Piglione ,  Hiroshi Suzuki

IPC: H04L12/56

CPC classification number: H04L47/6255 ,  H04L47/263 ,  H04L49/3018 ,  H04L49/3045

Abstract: In one implementation, an input queue switch provides latency fairness across multiple input ports and multiple output ports. In one embodiment, each input port maintains a virtual output queue for each associate output port. The virtual output queues across multiple inputs are aggregated for each specific output port. The sum of the lengths of the virtual output queues is compared to a threshold, and based on the comparison, feedback may be generated to control the operation of the input port for subsequent packets. The feedback may instruct the input port to stop buffering or drop packets destined for the output port with the sum of the lengths of the virtual output queues associated to the specific output port that exceeds the threshold. In another embodiment, each packet has an arrival timestamp, and a virtual output queue having the oldest timestamp is selected first to dequeue.

Abstract translation: 在一个实现中，输入队列交换机提供跨多个输入端口和多个输出端口的延迟公平性。 在一个实施例中，每个输入端口维护每个关联输出端口的虚拟输出队列。 跨多个输入的虚拟输出队列针对每个特定输出端口进行聚合。 将虚拟输出队列的长度的总和与阈值进行比较，并且基于比较，可以生成反馈以控制后续分组的输入端口的操作。 反馈可以指示输入端口以与超过阈值的特定输出端口相关联的虚拟输出队列的长度的总和来停止缓冲或丢弃目的地为输出端口的分组。 在另一个实施例中，每个分组具有到达时间戳，并且首先选择具有最早时间戳的虚拟输出队列以出队。