公开(公告)号：US20120100707A1

公开(公告)日：2012-04-26

申请号：US13280799

申请日：2011-10-25

Applicant: Choon-Kun RYU

Inventor： Choon-Kun RYU

IPC: H01L21/28

CPC classification number: H01L29/7926 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889

Abstract: A method for fabricating a non-volatile memory device with a three-dimensional structure includes forming a pipe gate conductive layer on a substrate, forming a pipe channel hole in the pipe gate conductive layer, burying a first sacrificial layer in the pipe channel hole, stacking interlayer dielectric layers and gate conductive layers on the pipe gate conductive layer including the first sacrificial layer, forming a pair of cell channel holes in the interlayer dielectric layers and the gate conductive layers, forming a second sacrificial layer on a resultant structure including the pair of cell channel holes, and forming a third sacrificial layer with etching selectivity relative to the second sacrificial layer on the second sacrificial layer and filling the cell channel holes with the third sacrificial layer.

Abstract translation: 一种用于制造具有三维结构的非易失性存储器件的方法包括在衬底上形成管栅极导电层，在管栅极导电层中形成管道通道孔，在管道孔中埋设第一牺牲层， 在包括第一牺牲层的管栅极导电层上层叠层间介质层和栅极导电层，在层间电介质层和栅极导电层中形成一对电池沟道孔，在包含该对的所得结构上形成第二牺牲层 的细胞通道孔，并且相对于第二牺牲层上的第二牺牲层形成具有蚀刻选择性的第三牺牲层，并且用第三牺牲层填充细胞通道孔。

公开(公告)号：US20130248806A1

公开(公告)日：2013-09-26

申请号：US13619653

申请日：2012-09-14

Applicant: Choon-Kun RYU

Inventor： Choon-Kun RYU

IPC: H01L45/00

CPC classification number: H01L45/08 ,  H01L45/145 ,  H01L45/1625

Abstract: A variable resistance memory device includes a first electrode, a second electrode, a first variable resistance layer formed over the first electrode and including at least two kinds of metal oxides, and a second variable resistance layer interposed between the first variable resistance layer and the second electrode and including a metal oxide.

Abstract translation: 可变电阻存储器件包括第一电极，第二电极，形成在第一电极上并包括至少两种金属氧化物的第一可变电阻层，以及介于第一可变电阻层和第二可变电阻层之间的第二可变电阻层 电极并且包括金属氧化物。