公开(公告)号：US20090269902A1

公开(公告)日：2009-10-29

申请号：US12499248

申请日：2009-07-08

申请人： Ho Jin CHO ,  Cheol Hwan PARK ,  Jae Soo KIM ,  Dong Kyun LEE

发明人： Ho Jin CHO ,  Cheol Hwan PARK ,  Jae Soo KIM ,  Dong Kyun LEE

IPC分类号： H01L21/02

CPC分类号： H01L28/65 ,  H01L27/10852 ,  H01L28/91

摘要： A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.

摘要翻译： 通过在具有存储节点接触插塞的半导体衬底上形成缓冲氧化物层，蚀刻停止层和模具绝缘层来制造电容器。 蚀刻模具绝缘层和蚀刻停止层，以在存储节点接触插塞的上部形成孔。 在包括孔的模具绝缘层上沉积渐缩层。 锥形层和缓冲氧化物层被回蚀刻，使得锥形层仅保留在蚀刻孔的上端部。 在剩余的锥形层上形成在蚀刻孔上的金属储存节点层。 去除模具绝缘层和剩余的锥形层以形成具有锥形上端的圆柱形存储节点。 在存储节点上形成介电层和板状节点。

公开(公告)号：US20090275186A1

公开(公告)日：2009-11-05

申请号：US12265759

申请日：2008-11-06

申请人： Cheol Hwan PARK ,  Ho Jin CHO ,  Jae Soo KIM ,  Dong Kyun LEE

发明人： Cheol Hwan PARK ,  Ho Jin CHO ,  Jae Soo KIM ,  Dong Kyun LEE

IPC分类号： H01L21/02

CPC分类号： H01L28/91

摘要： Forming a capacitor of a semiconductor device includes forming an interlayer dielectric having holes over a semiconductor substrate. A conductive layer is then formed on surfaces of the holes and on the upper surface of the interlayer dielectric. A silicon-containing conductive layer is formed by flowing a silicon source gas for the semiconductor substrate formed with the conductive layer, so that silicon atoms can penetrate into the conductive layer. The silicon-containing conductive layer prevents etchant from infiltrating the interlayer dielectric below the silicon-containing conductive layer.

摘要翻译： 形成半导体器件的电容器包括在半导体衬底上形成具有孔的层间电介质。 然后在孔的表面和层间电介质的上表面上形成导电层。 通过使形成有导电层的半导体衬底的硅源气体流动而形成含硅导电层，使得硅原子能够渗透到导电层中。 含硅导电层防止蚀刻剂渗透到含硅导电层之下的层间电介质。

公开(公告)号：US20080157093A1

公开(公告)日：2008-07-03

申请号：US11779093

申请日：2007-07-17

申请人： Ho Jin CHO ,  Cheol Hwan PARK ,  Jae Soo KIM ,  Dong Kyun LEE

发明人： Ho Jin CHO ,  Cheol Hwan PARK ,  Jae Soo KIM ,  Dong Kyun LEE

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L28/65 ,  H01L27/10852 ,  H01L28/91

摘要： A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.

摘要翻译： 通过在具有存储节点接触插塞的半导体衬底上形成缓冲氧化物层，蚀刻停止层和模具绝缘层来制造电容器。 蚀刻模具绝缘层和蚀刻停止层，以在存储节点接触插塞的上部形成孔。 在包括孔的模具绝缘层上沉积渐缩层。 锥形层和缓冲氧化物层被回蚀刻，使得锥形层仅保留在蚀刻孔的上端部。 在剩余的锥形层上形成在蚀刻孔上的金属储存节点层。 去除模具绝缘层和剩余的锥形层以形成具有锥形上端的圆柱形存储节点。 在存储节点上形成介电层和板状节点。

公开(公告)号：US20110024874A1

公开(公告)日：2011-02-03

申请号：US12647621

申请日：2009-12-28

申请人： Cheol Hwan PARK ,  Ho Jin CHO ,  Dong Kyun LEE

发明人： Cheol Hwan PARK ,  Ho Jin CHO ,  Dong Kyun LEE

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： A semiconductor device having a three-dimensional capacitor and a method for manufacturing the same is presented. The semiconductor device may have lower electrodes, a buffer layer, a dielectric layer, and an upper electrode. The lower electrodes are formed over a semiconductor substrate. The buffer layer is formed on sidewalls of the lower electrodes. The dielectric layer and an upper electrode are formed over semiconductor substrate including over the lower electrodes and the buffer layer. Accordingly, sufficient space between the lower electrodes can be secured. Furthermore, the lower electrodes can be each formed of a ruthenium layer and a titanium nitride layer and configured to have a pillar form. The dielectric layer may be composed of titanium dioxide.

摘要翻译： 本发明提供一种具有三维电容器的半导体器件及其制造方法。 半导体器件可以具有下电极，缓冲层，电介质层和上电极。 下电极形成在半导体衬底上。 缓冲层形成在下电极的侧壁上。 电介质层和上电极形成在包括在下电极和缓冲层之上的半导体衬底之上。 因此，可以确保下部电极之间的足够的空间。 此外，下电极可以由钌层和氮化钛层形成，并且被构造成具有柱状。 电介质层可以由二氧化钛构成。

公开(公告)号：US20100327410A1

公开(公告)日：2010-12-30

申请号：US12649610

申请日：2009-12-30

申请人： Cheol Hwan PARK ,  Ho Jin CHO ,  Dong Kyun LEE

发明人： Cheol Hwan PARK ,  Ho Jin CHO ,  Dong Kyun LEE

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10894

摘要： A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conductive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.

摘要翻译： 提出了具有高方位圆柱形电容器的半导体器件及其制造方法。 高档圆柱型电容器是一种稳定的结构，不容易造成保护环中的掩体缺陷和损失。 半导体器件包括圆柱形电容器结构，存储节点氧化物，保护环孔，导电层和封盖氧化物。 单元区域中的圆柱型电容器结构包括圆筒形下电极，电介质和上电极。 存储节点氧化物位于半导体衬底上的周边区域中。 导电层涂覆保护环孔。 在与半导体基板上的单元区域相邻的周边区域的边界处的保护环孔。 覆盖氧化物部分地填充导电层的一部分。 间隙填充膜填充在导电层的其余部分。

公开(公告)号：US20120019980A1

公开(公告)日：2012-01-26

申请号：US12979926

申请日：2010-12-28

申请人： Ho Jin CHO ,  Cheol Hwan PARK ,  Dong Kyun LEE

发明人： Ho Jin CHO ,  Cheol Hwan PARK ,  Dong Kyun LEE

IPC分类号： H01G4/06 ,  H01L21/02

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/90

摘要： An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.

摘要翻译： 本发明的实施例包括柱形电容器，其中柱形成在存储节点接触件的上部上。 底部电极形成在支柱的侧壁上，电介质膜形成在支柱和底部电极之上。 然后在电介质膜的上部上形成顶部电极。

公开(公告)号：US20110272784A1

公开(公告)日：2011-11-10

申请号：US13185873

申请日：2011-07-19

申请人： Cheol Hwan PARK ,  Ho Jin CHO ,  Dong Kyun LEE

发明人： Cheol Hwan PARK ,  Ho Jin CHO ,  Dong Kyun LEE

IPC分类号： H01L29/92

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10894

摘要： A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conducive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.

摘要翻译： 提出了具有高方位圆柱形电容器的半导体器件及其制造方法。 高档圆柱型电容器是一种稳定的结构，不容易造成保护环中的掩体缺陷和损失。 半导体器件包括圆柱形电容器结构，存储节点氧化物，保护环孔，导电层和封盖氧化物。 单元区域中的圆柱型电容器结构包括圆筒形下电极，电介质和上电极。 存储节点氧化物位于半导体衬底上的周边区域中。 导电层涂覆保护环孔。 在与半导体基板上的单元区域相邻的周边区域的边界处的保护环孔。 覆盖氧化物部分地填充导电层的一部分。 间隙填充膜填充在导电层的其余部分。

公开(公告)号：US20070236106A1

公开(公告)日：2007-10-11

申请号：US11688658

申请日：2007-03-20

申请人： Burhanettin KOC ,  Dong Kyun LEE ,  Jung Ho RYU ,  Byung Woo KANG

发明人： Burhanettin KOC ,  Dong Kyun LEE ,  Jung Ho RYU ,  Byung Woo KANG

IPC分类号： H01L41/00 ,  H01L41/083

CPC分类号： H01L41/0913 ,  H01L41/0471 ,  H01L41/0472 ,  H01L41/083 ,  H02N2/004 ,  H02N2/026

摘要： Provided is a piezoelectric vibrator that can finely drive a device by generating an elliptical motion using a combination of a longitudinal vibration and a flexural vibration. The piezoelectric vibrator can also provide high efficiency and be manufactured at low cost by using a simpler structure. The piezoelectric vibrator includes a piezoelectric element, first to third side electrodes, and a power transmission member. The piezoelectric element includes: a first piezoelectric element layer having a bisected top electrode formed thereon; a second piezoelectric element provided under the first piezoelectric element layer and having an internal ground electrode formed thereon; and a third piezoelectric element provided under the second piezoelectric element layer, the third piezoelectric element having an internal electrode symmetrical with the top electrode with respect to a stack plane, and a bottom electrode formed in a plane opposite to the plane where the internal electrode is formed. The first and second side electrodes electrically connect electrode patterns formed in a diagonal direction among the electrode patterns formed in the first and third piezoelectric element layers of the piezoelectric element, and the third side electrode electrically connects the internal ground electrode of the second piezoelectric element layer to the bottom electrode of the third piezoelectric element layer. The power transmission member is formed in one side of the piezoelectric element to transmit vibration generated from the piezoelectric element to the outside.

摘要翻译： 提供一种压电振动器，其可以通过使用纵向振动和弯曲振动的组合产生椭圆运动来微调驱动装置。 压电振动器还可以提供高效率并且通过使用更简单的结构以低成本制造。 压电振子包括压电元件，第一至第三侧面电极和电力传输构件。 压电元件包括​​：在其上形成有平分的顶部电极的第一压电元件层; 第二压电元件，设置在所述第一压电元件层的下方，并具有形成在其上的内部接地电极; 以及设置在所述第二压电元件层下方的第三压电元件，所述第三压电元件具有与所述顶部电极相对于堆叠平面对称的内部电极，以及底部电极，所述底部电极形成在与所述内部电极 形成。 第一和第二侧电极电连接形成在压电元件的第一和第三压电元件层中的电极图案中的沿对角线方向形成的电极图案，并且第三侧电极将第二压电元件层的内部接地电极 到第三压电元件层的底部电极。 动力传递部件形成在压电元件的一侧，以将从压电元件产生的振动传递到外部。