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    DETERMINATION OF SINGLE-FIX RECTIFICATION FUNCTION
    1.
    发明申请
    DETERMINATION OF SINGLE-FIX RECTIFICATION FUNCTION 有权
    单一修复功能的确定

    公开(公告)号：US20080288900A1

    公开(公告)日：2008-11-20

    申请号：US11841079

    申请日：2007-08-20

    申请人： Cheng-Ta Hsieh ,  Yifeng Wang ,  Yung-Te Lai ,  Chih-Chang Lin

    发明人： Cheng-Ta Hsieh ,  Yifeng Wang ,  Yung-Te Lai ,  Chih-Chang Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Some aspects provide determination of a function to rectify functional differences between netlist G1 and netlist G2 having inputs V. The determination may include determination of a signal s of netlist G1 that can be re-synthesized so as to correct the functional differences between netlist G1 and netlist G2, assignment of respective static values to a first plurality of inputs V, assignment of respective initial values to a second plurality of inputs V, determination of a first function based on the assigned static values, the assigned initial values, a first error function reflecting the difference between outputs of netlist G1 and netlist G2 for each vector of inputs V in a case that s equals 0, and a second error function reflecting the difference between the outputs of netlist G1 and netlist G2 for each vector of inputs V in a case that s equals 1. Also included may be determination of whether the first function rectifies the functional differences between netlist G1 and netlist G2, assignment, if it is determined that the first function does not rectify the functional differences, of respective next values to the second plurality of inputs, and determination of a second function based on the first function, the assigned static values, the assigned next values, the first error function, and the second error function.

    摘要翻译： 一些方面提供了确定具有输入V的网表G 1＆lt; 1＆gt;和网表G 2 2之间的功能差异的功能。该确定可以包括网表G的信号s的确定， 可以重新合成以便校正网表G 1和网表G 2 2之间的功能差异的SUB> 1 ，将各个静态值分配给 第一多个输入V，将各个初始值分配给第二多个输入V，基于所分配的静态值确定第一功能，分配的初始值，反映网表G 和网表G 2 。还包括确定 如果确定第一功能不排除功能差异，则第一功能是否纠正网表G 1＆lt; 1＆lt; 1＆gt;和网表G 2 2之间的功能差异， 相应的第二多个输入的下一个值，以及基于第一功能确定第二功能，分配的静态值，分配的下一个值，第一误差函数和第二误差函数。

    Determination of single-fix rectification function
    2.
    发明授权
    Determination of single-fix rectification function 有权
    确定单固定整流功能

    公开(公告)号：US07823104B2

    公开(公告)日：2010-10-26

    申请号：US11841079

    申请日：2007-08-20

    申请人： Cheng-Ta Hsieh ,  Yifeng Wang ,  Yung-Te Lai ,  Chih-Chang Lin

    发明人： Cheng-Ta Hsieh ,  Yifeng Wang ,  Yung-Te Lai ,  Chih-Chang Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Some aspects provide determination of a function to rectify functional differences between netlist G1 and netlist G2 having inputs V. The determination may include determination of a signal s of netlist G1 that can be re-synthesized so as to correct the functional differences between netlist G1 and netlist G2, assignment of respective static values to a first plurality of inputs V, assignment of respective initial values to a second plurality of inputs V, determination of a first function based on the assigned static values, the assigned initial values, a first error function reflecting the difference between outputs of netlist G1 and netlist G2 for each vector of inputs V in a case that s equals 0, and a second error function reflecting the difference between the outputs of netlist G1 and netlist G2 for each vector of inputs V in a case that s equals 1. Also included may be determination of whether the first function rectifies the functional differences between netlist G1 and netlist G2, assignment, if it is determined that the first function does not rectify the functional differences, of respective next values to the second plurality of inputs, and determination of a second function based on the first function, the assigned static values, the assigned next values, the first error function, and the second error function.

    摘要翻译： 一些方面提供了确定具有输入V的网表G1和网表G2之间的功能差异的功能。该确定可以包括确定可以被重新合成的网表G1的信号s，以便校正网表G1和网表G1之间的功能差异 网表G2，将各个静态值分配给第一多个输入V，将各个初始值分配给第二多个输入V，基于分配的静态值确定第一函数，分配的初始值，第一误差函数 反映在s等于0的情况下，对于输入V的每个向量的网表G1和网表G2的输出之间的差异，以及反映网格列表G1和网表G2的输出之间的差异的第二误差函数， s等于1的情况。还包括确定第一功能是否整理网表G1和网表之间的功能差异 G2，如果确定第一功能不排除与第二多个输入相对应的下一个值的功能差异，以及基于第一功能确定第二功能，分配的静态值，分配的下一个 值，第一个错误函数和第二个错误函数。

    Combinational equivalence checking methods and systems with internal don't cares
    3.
    发明授权
    Combinational equivalence checking methods and systems with internal don't cares 有权
    组合等价检查方法和内部系统不需要关心

    公开(公告)号：US06842884B2

    公开(公告)日：2005-01-11

    申请号：US10230976

    申请日：2002-08-28

    申请人： Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

    发明人： Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F17/504

    摘要： An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuits are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.

    摘要翻译： 等价检查方法提供第一和第二逻辑功能。 不要在第一和第二逻辑功能中插入无门的条件。 无关门的插入产生第一中间电路和第二中间电路。 当3DC门和SDC门共存在第一和第二中间电路中时，第一中间电路的所有3DC门被传播并合并成单个3DC门。 当3DC门和SDC门共存在第一和第二中间电路中时，第二中间电路的所有3DC门都被传播并合并成单个3DC门。 响应于3DC门的传播和合并产生第一和第二电路。 然后在不同的等价关系下对第二电路执行第一电路的组合等价检查。

    Method and system for logic equivalence checking
    4.
    发明授权
    Method and system for logic equivalence checking 有权
    逻辑等价检查方法和系统

    公开(公告)号：US07266790B2

    公开(公告)日：2007-09-04

    申请号：US10656801

    申请日：2003-09-04

    申请人： Manish Pandey ,  Yung-Te Lai ,  Bret Siarkowski ,  Kei-Yong Khoo ,  Chih-Chang Lin

    发明人： Manish Pandey ,  Yung-Te Lai ,  Bret Siarkowski ,  Kei-Yong Khoo ,  Chih-Chang Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/504

    摘要： Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

    摘要翻译： 一些实施例涉及一种用于使用基于包含从先前等效检查运行解决的子问题的信息的持久高速缓存来执行使用自适应学习的电路的逻辑等价性检查（EC）的方法和装置。 这些子问题可以包括基本的EC任务，例如逻辑锥比较和/或状态元素映射。

    Method and System for Logic Equivalence Checking
    5.
    发明申请
    Method and System for Logic Equivalence Checking 有权
    逻辑等价检查方法与系统

    公开(公告)号：US20070294649A1

    公开(公告)日：2007-12-20

    申请号：US11847177

    申请日：2007-08-29

    申请人： Manish Pandey ,  Yung-Te Lai ,  Bret Siarkowski ,  Kei-Yong Khoo ,  Chih-Chang Lin

    发明人： Manish Pandey ,  Yung-Te Lai ,  Bret Siarkowski ,  Kei-Yong Khoo ,  Chih-Chang Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/504

    摘要： Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

    摘要翻译： 一些实施例涉及一种用于使用基于包含从先前等效检查运行解决的子问题的信息的持久高速缓存来执行使用自适应学习的电路的逻辑等价性检查（EC）的方法和装置。 这些子问题可以包括基本的EC任务，例如逻辑锥比较和/或状态元素映射。

    Combinational equivalence checking methods and systems with internal don't cares
    6.
    发明申请
    Combinational equivalence checking methods and systems with internal don't cares 有权
    组合等价检查方法和内部系统不需要关心

    公开(公告)号：US20050155002A1

    公开(公告)日：2005-07-14

    申请号：US10995658

    申请日：2004-11-22

    申请人： Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

    发明人： Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F17/504

    摘要： An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuit are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.

    摘要翻译： 等价检查方法提供第一和第二逻辑功能。 不要在第一和第二逻辑功能中插入无门的条件。 无关门的插入产生第一中间电路和第二中间电路。 当3DC门和SDC门共存在第一和第二中间电路中时，第一中间电路的所有3DC门被传播并合并成单个3DC门。 当3DC门和SDC门共存在第一和第二中间电路中时，第二中间电路的所有3DC门都被传播并合并成单个3DC门。 响应于3DC门的传播和合并而产生第一和第二电路。 然后在不同的等价关系下对第二电路执行第一电路的组合等价检查。

    Method and system for logic equivalence checking
    8.
    发明授权
    Method and system for logic equivalence checking 有权
    逻辑等价检查方法和系统

    公开(公告)号：US07620918B2

    公开(公告)日：2009-11-17

    申请号：US11847177

    申请日：2007-08-29

    申请人： Manish Pandey ,  Yung-Te Lai ,  Bret Siarowski ,  Kei-Yong Khoo ,  Chih-Chang Lin

    发明人： Manish Pandey ,  Yung-Te Lai ,  Bret Siarowski ,  Kei-Yong Khoo ,  Chih-Chang Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/504

    摘要： Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

    摘要翻译： 一些实施例涉及一种用于使用基于包含从先前等效检查运行解决的子问题的信息的持久高速缓存来执行使用自适应学习的电路的逻辑等价性检查（EC）的方法和装置。 这些子问题可以包括基本的EC任务，例如逻辑锥比较和/或状态元素映射。

    Combinational equivalence checking methods and systems with internal don't cares
    10.
    发明授权
    Combinational equivalence checking methods and systems with internal don't cares 有权
    组合等价检查方法和内部系统不需要关心

    公开(公告)号：US07240311B2

    公开(公告)日：2007-07-03

    申请号：US10995658

    申请日：2004-11-22

    申请人： Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

    发明人： Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F17/504

    摘要： An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuit are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.

    摘要翻译： 等价检查方法提供第一和第二逻辑功能。 不要在第一和第二逻辑功能中插入无门的条件。 无关门的插入产生第一中间电路和第二中间电路。 当3DC门和SDC门共存在第一和第二中间电路中时，第一中间电路的所有3DC门被传播并合并成单个3DC门。 当3DC门和SDC门共存在第一和第二中间电路中时，第二中间电路的所有3DC门都被传播并合并成单个3DC门。 响应于3DC门的传播和合并而产生第一和第二电路。 然后在不同的等价关系下对第二电路执行第一电路的组合等价检查。