公开(公告)号：US07620764B2

公开(公告)日：2009-11-17

申请号：US11768113

申请日：2007-06-25

Applicant: Charle′ R. Rupp

Inventor： Charle′ R. Rupp

IPC: G06F13/00 ,  G06F9/00

CPC classification number: G06F7/762 ,  G06F5/015 ,  G06F7/768 ,  G06F13/4022

Abstract: A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo routing circuit is formed upon a semiconductor substrate and routes data among a number of reconfigurable computational elements. The silo routing circuit comprises a plurality of input terminals and a plurality of output terminals. Further, the silo routing circuit includes a multi-stage interconnection network (“MIN”) of switches configurable to form data paths from any input terminal to any output terminal.

Abstract translation: 一种用于在可重配置逻辑元件之间通过较少的交换机和互连路由数据的系统，装置和方法，并且用于调整路由资源以动态地执行诸如移位和位反转操作之类的复杂位级排列。 在一个实施例中，示例性筒仓路由电路形成在半导体衬底上并在多个可重新配置的计算元件之间路由数据。 筒仓路由电路包括多个输入端子和多个输出端子。 此外，筒仓路由电路包括可配置为形成从任何输入端到任何输出端的数据路径的开关的多级互连网络（“MIN”）。

公开(公告)号：US07062520B2

公开(公告)日：2006-06-13

申请号：US09883976

申请日：2001-06-19

Applicant: Charle′ R. Rupp

Inventor： Charle′ R. Rupp

IPC: G06F7/38

CPC classification number: H03K19/17796 ,  H03K19/17728

Abstract: A novel architecture for a multi-scale programmable logic array (MSA) to be used in the design of complex digital systems allows digital logic to be programmed using both small-scale blocks (also called gate level blocks) as well as medium scale blocks (also called Register Transfer Level or RTL blocks). The MSA concept is based on a bit sliceable Arithmetic Logic Unit (ALU). Each bit-slice may be programmed to perform a basic Boolean logic operation or may be programmed to contribute to higher-level functions that are further programmed by an ALU controller circuit. The ALU controller level in this new approach also allows the primitive logic operations computed at the bit-slice level to be combined to perform complex random logic operations. The data shifting capability of this new programmable logic architecture reduces the complexity of the programmable routing needed to implement shift operations including multiplier arrays. The new array also allows logic variables under program control to dynamically modify the micro-program of each ALU. This technique is called configuration overlay and simplifies the programming of complex arithmetic and random logic functions.

Abstract translation: 用于复杂数字系统设计中的多尺度可编程逻辑阵列（MSA）的新型架构允许使用小规模块（也称为门级块）以及中等尺度块来编程数字逻辑（ 也称为寄存器传输级别或RTL块）。 MSA概念基于可分位的算术逻辑单元（ALU）。 每个位片可以被编程以执行基本的布尔逻辑运算，或者可以被编程为有助于由ALU控制器电路进一步编程的更高级的功能。 这种新方法中的ALU控制器级别还允许在位片级别计算的原始逻辑运算被组合以执行复杂的随机逻辑运算。 这种新的可编程逻辑架构的数据移动能力降低了实现包括乘法器阵列在内的移位操作所需的可编程路由的复杂性。 新阵列还允许程序控制下的逻辑变量动态修改每个ALU的微程序。 这种技术称为配置覆盖，简化了复杂算术和随机逻辑功能的编程。

公开(公告)号：US07526632B1

公开(公告)日：2009-04-28

申请号：US10971372

申请日：2004-10-22

Applicant: Charle′ R. Rupp ,  Jeffrey M. Arnold

Inventor： Charle′ R. Rupp ,  Jeffrey M. Arnold

IPC: G06F15/00 ,  G06F15/76

CPC classification number: G06F9/30181 ,  G06F9/30003 ,  G06F9/3001 ,  G06F9/3885 ,  G06F9/3897 ,  G06F15/7867

Abstract: A system, apparatus and a method for implementing multifunctional memories is disclosed. The multifunctional memories perform a variety of functions during execution of extended instructions in a reconfigurable data path processor composed of processing nodes. In one embodiment, a processing node can be comprised of modular processing elements to perform computations associated with an extended instruction. Also, such a node includes at least two multifunctional memories and a data flow director configured to selectably couple the first multifunctional memory and the second multifunctional memory. The data flow director is configured to route data out from a first multifunctional memory of the two multifunctional memories while data is being routed into a second multifunctional memory. In another embodiment, a processing node is configured to compute a function output based on a number of Boolean functions, wherein at least one of the multifunctional memories is configured as a look-up table (“LUT”).

Abstract translation: 公开了一种用于实现多功能存储器的系统，装置和方法。 多功能存储器在由处理节点组成的可重构数据路径处理器中执行扩展指令期间执行各种功能。 在一个实施例中，处理节点可以由模块化处理元件组成，以执行与扩展指令相关联的计算。 此外，这种节点包括至少两个多功能存储器和配置成可选择地耦合第一多功能存储器和第二多功能存储器的数据流导向器。 数据流导向器被配置为在数据被路由到第二多功能存储器的同时从两个多功能存储器的第一多功能存储器路由数据。 在另一个实施例中，处理节点被配置为基于多个布尔函数来计算功能输出，其中多功能存储器中的至少一个被配置为查找表（“LUT”）。