公开(公告)号：US20150055552A1

公开(公告)日：2015-02-26

申请号：US14040814

申请日：2013-09-30

Applicant: BROADCOM CORPORATION

Inventor： Alireza Tarighat Mehrabani ,  Behzad Nourani

IPC: H04W24/08 ,  H04L25/03 ,  H04L7/033

CPC classification number: H04L7/0331 ,  H03L7/197 ,  H03L7/1974 ,  H03L7/1976 ,  H04L27/00

Abstract: A method and system is includes configurable carrier phase noise shaping. A fractional phase locked loop (PLL) uses a bank of delta-sigma modulators (DSM) to generate fractional ratios of the reference signal frequency. The bank of delta-sigma modulators provides for dynamic adjustments in the fractional PLL based phase noise performance of the communications network. The bank of DSMs is designed such that they have different and conflicting phase noise profiles. The communication network parameters are monitored and utilized for selecting a specific DSM from the bank of DSMs which most closely resembles a desired communications network phase noise profile.

Abstract translation: 一种方法和系统包括可配置载波相位噪声整形。 分数锁相环（PLL）使用一组Δ-Σ调制器（DSM）来产生参考信号频率的分数比。 Delta-sigma调制器组提供通信网络基于分数PLL的相位噪声性能的动态调整。 帝斯曼银行的设计使得它们具有不同的和冲突的相位噪声分布。 通信网络参数被监控并用于从最相似类似于期望的通信网络相位噪声分布图的DSM集群中选择特定的DSM。

公开(公告)号：US09041444B1

公开(公告)日：2015-05-26

申请号：US14109498

申请日：2013-12-17

Applicant: Broadcom Corporation

Inventor： Alireza Tarighat Mehrabani ,  Behzad Nourani

IPC: H03L7/06 ,  H03L7/00

CPC classification number: H03L7/00 ,  H03L7/0805 ,  H03L7/1976

Abstract: Methods, systems, and apparatuses are described for compensating for an undesired fractional spur due to a PLL in a communication system. The communication system includes a time-to-digital converter (TDC) that is configured to execute in parallel to the PLL. The TDC is configured to determine a phase difference between a reference frequency and an output oscillation signal provided by the PLL. The phase difference is received by a processor to estimate particular characteristics of the undesired fractional spur, and the estimate of the characteristics is used to construct an estimate of the undesired fractional spur.

Abstract translation: 描述了用于补偿由通信系统中的PLL引起的不期望的分数杂散的方法，系统和装置。 通信系统包括被配置为与PLL并行执行的时间 - 数字转换器（TDC）。 TDC被配置为确定由PLL提供的参考频率和输出振荡信号之间的相位差。 相位差由处理器接收以估计不想要的分数支线的特定特性，并且使用特征的估计来构造不期望的分数支线的估计。

公开(公告)号：US20150145568A1

公开(公告)日：2015-05-28

申请号：US14109498

申请日：2013-12-17

Applicant: Broadcom Corporation

Inventor： Alireza Tarighat Mehrabani ,  Behzad Nourani

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03L7/0805 ,  H03L7/1976

Abstract: Methods, systems, and apparatuses are described for compensating for an undesired fractional spur due to a PLL in a communication system. The communication system includes a time-to-digital converter (TDC) that is configured to execute in parallel to the PLL. The TDC is configured to determine a phase difference between a reference frequency and an output oscillation signal provided by the PLL. The phase difference is received by a processor to estimate particular characteristics of the undesired fractional spur, and the estimate of the characteristics is used to construct an estimate of the undesired fractional spur.

Abstract translation: 描述了用于补偿由通信系统中的PLL引起的不期望的分数杂散的方法，系统和装置。 通信系统包括被配置为与PLL并行执行的时间 - 数字转换器（TDC）。 TDC被配置为确定由PLL提供的参考频率和输出振荡信号之间的相位差。 相位差由处理器接收以估计不想要的分数支线的特定特性，并且使用特征的估计来构造不期望的分数支线的估计。