公开(公告)号：US20190115933A1

公开(公告)日：2019-04-18

申请号：US16153474

申请日：2018-10-05

Applicant: British Cayman Islands Intelligo Technology Inc.

Inventor： Chi-Hao Chen ,  Hong-Ching Chen ,  Chun-Ming Huang ,  Tsung-Liang Chen

IPC: H03M7/30 ,  G06F7/544 ,  G06F17/16 ,  G06N3/04 ,  H03K19/20

Abstract: An acceleration apparatus applied in an artificial neuron is disclosed. The acceleration apparatus comprises an AND gate array, a first storage device, a second storage device and a multiply-accumulate (MAC) circuit. The AND gate array with plural AND gates receives a first bitmap and a second bitmap to generate an output bitmap. The first storage device stores a first payload and outputs a corresponding non-zero first element according to a first access address associated with a result of comparing the first bitmap with the output bitmap. The second storage device stores a second payload and outputs a corresponding non-zero second element according to a second access address associated with a result of comparing the second bitmap with the output bitmap. The MAC circuit calculates a dot product of two element sequences from the first storage device and the second storage device.

公开(公告)号：US11068775B2

公开(公告)日：2021-07-20

申请号：US15910404

申请日：2018-03-02

Applicant: British Cayman Islands Intelligo Technology Inc.

Inventor： Hong-Ching Chen ,  Chun-Ming Huang ,  Chi-Hao Chen ,  Tsung-Liang Chen

IPC: G06N3/06 ,  G06N3/063

Abstract: A processing apparatus applied in an artificial neuron is disclosed. The processing apparatus comprises a parser, a lookup array, a summing circuit and a MAC circuit. The parser parses one of M packets to extract a non-zero weight value from a header of the one packet, to identify a plurality of bit positions with a specified digit from a payload of the one packet, and to output the non-zero weight value and the bit positions in parallel. The lookup array contains N synapse values and is indexed by the bit positions in parallel to generate a plurality of match values. The summing circuit sums up the match values to generate a sum value. The MAC circuit generates a product of the non-zero weight value and the sum value, and generates an accumulate value based on the product and at least one previous accumulate value.