公开(公告)号：US20070226739A1

公开(公告)日：2007-09-27

申请号：US11317468

申请日：2005-12-22

Applicant: Dan Dodge ,  Attila Danko ,  Sebastien Marineau-Mes ,  Peter Veen ,  Colin Burgess ,  Thomas Fletcher ,  Brian Stecher

Inventor： Dan Dodge ,  Attila Danko ,  Sebastien Marineau-Mes ,  Peter Veen ,  Colin Burgess ,  Thomas Fletcher ,  Brian Stecher

IPC: G06F9/46

CPC classification number: G06F9/5038 ,  G06F9/4881 ,  G06F9/4887 ,  G06F9/505 ,  G06F9/5077

Abstract: A system is set forth that comprises a processor, such as a single processor or symmetric multiprocessor, and one or more memory storage units. The system also includes software code that is stored in the memory storage units. The software code is executable by the processor and comprises code for generating a plurality of adaptive partitions that are each associated with one or more software threads. Each of the adaptive partitions has a corresponding processor budget. The code also is executable to generate at least one sending thread and at least one receiving thread. The receiving thread responds to communications from the sending thread to execute one or more tasks corresponding to the communications. A scheduling system also forms at least part of the code that is executable by the processor. In operation, the scheduling system selectively allocates the processor to each sending and receiving thread based, at least in part, on the processor budget of the adaptive partition associated with the respective thread. In this type of sending/receiving environment, the scheduling system bills the processor budget of the adaptive partition associated with the sending thread for processor allocation used by the receiving thread to respond to communications sent by the sending thread.

Abstract translation: 提出了一种包括诸如单个处理器或对称多处理器的处理器以及一个或多个存储器存储单元的系统。 该系统还包括存储在存储器单元中的软件代码。 软件代码可由处理器执行，并且包括用于生成与一个或多个软件线程相关联的多个自适应分区的代码。 每个自适应分区具有相应的处理器预算。 代码也是可执行的，以生成至少一个发送线程和至少一个接收线程。 接收线程响应来自发送线程的通信，以执行与通信相对应的一个或多个任务。 调度系统还形成可由处理器执行的代码的至少一部分。 在操作中，调度系统至少部分地基于与相应线程相关联的自适应分区的处理器预算来选择性地将处理器分配给每个发送和接收线程。 在这种发送/接收环境中，调度系统对与发送线程相关联的自适应分区的处理器预算进行计费，以便接收线程使用的处理器分配来响应发送线程发送的通信。

公开(公告)号：US20060206881A1

公开(公告)日：2006-09-14

申请号：US11371638

申请日：2006-03-08

Applicant: Dan Dodge ,  Attilla Danko ,  Sebastien Marineau-Mes ,  Peter van der Veen ,  Colin Burgess ,  Thomas Fletcher ,  Brian Stecher

Inventor： Dan Dodge ,  Attilla Danko ,  Sebastien Marineau-Mes ,  Peter van der Veen ,  Colin Burgess ,  Thomas Fletcher ,  Brian Stecher

IPC: G06F9/45

CPC classification number: G06F9/4881

Abstract: A system is set forth that includes a processor, one or more memory storage units, and software code stored in the one or more memory storage units. The software code is executable by the processor to generate a plurality of adaptive partitions that are each associated with one or more process threads. Each of the plurality of adaptive partitions has a corresponding processor time budget. One or more of the process threads are designated as critical threads. Each adaptive partition associated with a critical thread is assigned a corresponding critical time budget. The software code also includes a scheduling system that is executable by the processor for selectively allocating the processor to run the process threads based, at least in part, on the processor time budgets of the respective adaptive partitions. The scheduling system may allocate the processor to run a critical thread based on the available critical time budget of the associated adaptive partition even when the processor time budget of the associated adaptive partition has been exhausted. In one example, the scheduling system functions SO that it only bills the critical time budget of an adaptive partition for time used to run an associated critical thread when the processor is overloaded and the critical time budget for the adaptive partition is concurrently exhausted. Methods of implementing such a system are also set forth.

Abstract translation: 提出了一种包括处理器，一个或多个存储器单元和存储在一个或多个存储器存储单元中的软件代码的系统。 软件代码可由处理器执行以产生多个与一个或多个进程线程相关联的自适应分区。 多个自适应分区中的每一个具有对应的处理器时间预算。 一个或多个进程线程被指定为关键线程。 与关键线程相关联的每个自适应分区都被分配相应的关键时间预算。 软件代码还包括调度系统，其可由处理器执行，用于至少部分地基于相应自适应分区的处理器时间预算来选择性地分配处理器来运行处理线程。 即使相关联的自适应分区的处理器时间预算已经耗尽，调度系统也可以基于相关自适应分区的可用关键时间预算来分配处理器来运行关键线程。 在一个示例中，调度系统的功能是，当处理器过载时，它仅对用于运行相关联的关键线程的时间用于自适应分区的关键时间预算并且同时耗尽自适应分区的关键时间预算。 还阐述了实现这种系统的方法。

公开(公告)号：US07870554B2

公开(公告)日：2011-01-11

申请号：US11371634

申请日：2006-03-08

Applicant: Dan Dodge ,  Attilla Danko ,  Sebastien Marineau-Mes ,  Peter van der Veen ,  Colin Burgess ,  Thomas Fletcher ,  Brian Stecher

Inventor： Dan Dodge ,  Attilla Danko ,  Sebastien Marineau-Mes ,  Peter van der Veen ,  Colin Burgess ,  Thomas Fletcher ,  Brian Stecher

IPC: G06F9/46

CPC classification number: G06F9/4881

Abstract: A system includes a processor, one or more memory storage units, and software code stored in the memory storage units. The software code is executable by the processor to generate a plurality of adaptive partitions that are each associated with one or more process threads. Each of adaptive partition has one or more corresponding assigned scheduling attributes. The software code includes a scheduling system for selectively allocating the processor to run process threads based on a comparison between ordering function values for each adaptive partition. Ordering function values are calculated based on scheduling attributes of the corresponding adaptive partition. A critical ordering function value also may be calculated and used to determine the proper manner of billing an associated adaptive partition for the processor allocation used to run its associated critical threads. Methods of implementing various aspects of such a system are also set forth.

Abstract translation: 系统包括处理器，一个或多个存储器单元和存储在存储器存储单元中的软件代码。 软件代码可由处理器执行以产生多个与一个或多个进程线程相关联的自适应分区。 每个自适应分区具有一个或多个相应的分配的调度属性。 该软件代码包括一个调度系统，用于基于每个自适应分区的排序函数值之间的比较来选择性地分配处理器来运行处理线程。 根据相应自适应分区的调度属性计算订购功能值。 关键排序函数值也可以被计算并用于确定用于运行其相关联的关键线程的处理器分配的相关自适应分区的适当的计费方式。 还阐述了实现这种系统的各个方面的方法。

公开(公告)号：US20090019254A1

公开(公告)日：2009-01-15

申请号：US11776970

申请日：2007-07-12

Applicant: Brian Stecher

Inventor： Brian Stecher

IPC: G06F12/00

CPC classification number: G06F12/1027 ,  G06F2212/652

Abstract: A processing system includes memory management software responsive to a translation lookaside buffer miss. The memory management software updates translation lookaside buffer information based on one or more missed virtual addresses. Entries of a first translation lookaside buffer are updated by the memory management software with information corresponding to the missed virtual addresses if memory page size information for the missed virtual addresses meet a first criterion. Entries of a second translation lookaside buffer are updated by the memory management software with information corresponding to the missed virtual addresses if memory page size information for the missed virtual addresses meet a second criterion. The first and second criterion may correspond to first and second memory page sizes supported by the respective translation lookaside buffers.

Abstract translation: 处理系统包括响应于翻译后备缓存器未命中的存储器管理软件。 存储器管理软件基于一个或多个错过的虚拟地址更新翻译后备缓冲器信息。 如果缺失的虚拟地址的存储器页面大小信息满足第一准则，则由存储器管理软件更新与虚拟虚拟地址相对应的信息的第一翻译后备缓冲器的条目。 如果缺失的虚拟地址的存储器页面尺寸信息满足第二准则，则由存储器管理软件更新与错过的虚拟地址相对应的信息的第二翻译后备缓冲器的条目。 第一和第二标准可以对应于由相应的翻译后备缓冲器支持的第一和第二存储器页面大小。

公开(公告)号：US20090019253A1

公开(公告)日：2009-01-15

申请号：US11776967

申请日：2007-07-12

Applicant: Brian Stecher ,  Hao Zhou ,  Sunil Kittur

Inventor： Brian Stecher ,  Hao Zhou ,  Sunil Kittur

IPC: G06F12/02

CPC classification number: G06F12/04 ,  G06F12/1027 ,  G06F12/1458 ,  G06F2212/652

Abstract: A processing system includes memory management software responsive to changes in a page table. The memory management software consolidates contiguous page table entries into one or more page table entries that have larger memory page sizes. The memory management software updates the entries of a translation lookaside buffer that correspond to the consolidated contiguous page table entries.

Abstract translation: 处理系统包括响应于页表中的变化的存储器管理软件。 内存管理软件将连续页表条目合并到一个或多个具有较大内存页大小的页表条目中。 存储器管理软件更新对应于合并的连续页表条目的翻译后备缓冲器的条目。

公开(公告)号：US20070061788A1

公开(公告)日：2007-03-15

申请号：US11371634

申请日：2006-03-08

Applicant: Dan Dodge ,  Attilla Danko ,  Sebastien Marineau-Mes ,  Peter Veen ,  Colin Burgess ,  Thomas Fletcher ,  Brian Stecher

Inventor： Dan Dodge ,  Attilla Danko ,  Sebastien Marineau-Mes ,  Peter Veen ,  Colin Burgess ,  Thomas Fletcher ,  Brian Stecher

IPC: G06F9/45

CPC classification number: G06F9/4881

Abstract: A system is set forth that includes a processor, one or more memory storage units, and software code stored in the one or more memory storage units. The software code is executable by the processor to generate a plurality of adaptive partitions that are each associated with one or more process threads. Each of the plurality of adaptive partitions has one or more corresponding scheduling attributes that are assigned to it. The software code further includes a scheduling system that is executable by the processor for selectively allocating the processor to run the process threads based on a comparison between ordering function values for each adaptive partition. The ordering function value for each adaptive partition is calculated using one or more of the scheduling attributes of the corresponding adaptive partition. The scheduling attributes that may be used to calculate the ordering function value include, for example, 1) the process budget, such as a guaranteed time budget, of the adaptive partition, 2) the critical budget, if any, of the adaptive partition, 3) the rate at which the process threads of an adaptive partition consume processor time, or the like. For each adaptive partition that is associated with a critical thread, a critical ordering function value also may be calculated. The scheduling system may compare the ordering function value with the critical ordering function value of the adaptive partition to determine the proper manner of billing the adaptive partition for the processor allocation used to run its associated critical threads. Methods of implementing various aspects of such a system are also set forth.

Abstract translation: 提出了一种包括处理器，一个或多个存储器单元和存储在一个或多个存储器存储单元中的软件代码的系统。 软件代码可由处理器执行以产生多个与一个或多个进程线程相关联的自适应分区。 多个自适应分区中的每一个具有分配给它的一个或多个对应的调度属性。 软件代码还包括可由处理器执行的调度系统，用于基于每个自适应分区的排序函数值之间的比较来选择性地分配处理器来运行处理线程。 使用相应自适应分区的一个或多个调度属性来计算每个自适应分区的排序函数值。 可用于计算排序函数值的调度属性包括例如1）自适应分区的过程预算，例如保证时间预算，2）自适应分区的关键预算（如果有的话） 3）自适应分区的进程线程消耗处理器时间的速率等。 对于与关键线程相关联的每个自适应分区，也可以计算临界排序函数值。 调度系统可以将排序函数值与自适应分区的关键排序函数值进行比较，以确定用于运行其关联关键线程的处理器分配的自适应分区计费的适当方式。 还阐述了实现这种系统的各个方面的方法。

公开(公告)号：US08327112B2

公开(公告)日：2012-12-04

申请号：US13018492

申请日：2011-02-01

Applicant: Brian Stecher

Inventor： Brian Stecher

IPC: G06F12/08

CPC classification number: G06F12/1036 ,  G06F2212/652

Abstract: A processing system includes a page table including a plurality of page table entries. Each of the plurality of page table entries includes information for translating a virtual address page to a corresponding physical address page. The processing system also includes a translation lookaside buffer adapted to cache page table information. The processing system also includes memory management software responsive to changes in the page table to consolidate a run of contiguous page table entries into one or more page table entries having a larger memory page size, Y. The memory management software further determines whether the run of contiguous page table entries may be cached in an entry of the translation lookaside buffer that caches multiple page table entries, X, in a single translation lookaside buffer entry.

Abstract translation: 处理系统包括包括多个页表项的页表。 多个页表条目中的每一个包括用于将虚拟地址页转换到对应的物理地址页的信息。 处理系统还包括适于缓存页表信息的翻译后备缓冲器。 处理系统还包括响应于页表中的变化的存储器管理软件，以将连续页表条目的运行合并到具有较大存储器页大小的一个或多个页表项中。存储器管理软件还确定是否运行 连续页表条目可以被缓存在翻译后备缓冲器的条目中，该条目在单个翻译后备缓冲器条目中高速缓存多个页表条目X。

公开(公告)号：US20110107342A1

公开(公告)日：2011-05-05

申请号：US12978083

申请日：2010-12-23

Applicant: Dan Dodge ,  Attilla Danko ,  Sebastien Marineau-Mes ,  Peter van der Veen ,  Colin Burgess ,  Thomas Fletcher ,  Brian Stecher

Inventor： Dan Dodge ,  Attilla Danko ,  Sebastien Marineau-Mes ,  Peter van der Veen ,  Colin Burgess ,  Thomas Fletcher ,  Brian Stecher

IPC: G06F9/46

CPC classification number: G06F9/4881

Abstract: A system is set forth that includes a processor, one or more memory storage units, and software code stored in the one or more memory storage units. The software code is executable by the processor to generate a plurality of adaptive partitions that are each associated with one or more process threads. Each of the plurality, of adaptive partitions has one or more corresponding scheduling attributes that are assigned to it. The software code further includes a scheduling system that is executable by the processor for selectively allocating the processor to run the process threads based on a comparison between ordering function values for each adaptive partition. The ordering function value for each adaptive partition is calculated using one or more of the scheduling attributes of the corresponding adaptive partition. The scheduling attributes that may be used to calculate the ordering function value include, for example, 1) the process budget, such as a guaranteed time budget, of the adaptive partition, 2) the critical budget, if any, of the adaptive partition, 3) the rate at which the process threads of an adaptive partition consume processor time, or the like. For each adaptive partition that is associated with a critical thread, a critical ordering function value also may be calculated. The scheduling system may compare the ordering function value with the critical ordering function value of the adaptive partition to determine the proper manner of billing the adaptive partition for the processor allocation used to run its associated critical threads. Methods of implementing various aspects of such a system are also set forth.

Abstract translation: 提出了一种包括处理器，一个或多个存储器单元和存储在一个或多个存储器存储单元中的软件代码的系统。 软件代码可由处理器执行以产生多个与一个或多个进程线程相关联的自适应分区。 多个自适应分区中的每一个具有分配给它的一个或多个对应的调度属性。 软件代码还包括可由处理器执行的调度系统，用于基于每个自适应分区的排序函数值之间的比较来选择性地分配处理器来运行处理线程。 使用相应自适应分区的一个或多个调度属性来计算每个自适应分区的排序函数值。 可用于计算排序函数值的调度属性包括例如1）自适应分区的过程预算，例如保证时间预算，2）自适应分区的关键预算（如果有的话） 3）自适应分区的进程线程消耗处理器时间的速率等。 对于与关键线程相关联的每个自适应分区，也可以计算临界排序函数值。 调度系统可以将排序函数值与自适应分区的关键排序函数值进行比较，以确定用于运行其关联关键线程的处理器分配的自适应分区计费的适当方式。 还阐述了实现这种系统的各个方面的方法。

公开(公告)号：US07917725B2

公开(公告)日：2011-03-29

申请号：US11853451

申请日：2007-09-11

Applicant: Brian Stecher

Inventor： Brian Stecher

IPC: G06F12/08

CPC classification number: G06F12/1036 ,  G06F2212/652

Abstract: A processing system includes memory management software responsive to changes in a page table to consolidate a run of contiguous page table entries into a page table entry having a larger memory page size. The memory management software determines whether the run of contiguous page table entries may be cached using the larger memory page size in an entry of a translation lookaside buffer. The translation lookaside buffer may be a MIPS-like TLB in which multiple page table entries are cached in each TLB entry.

Abstract translation: 处理系统包括响应于页表中的变化的存储器管理软件，以将连续页表项的运行合并到具有较大存储器页大小的页表项中。 存储器管理软件确定在翻译后备缓冲器的条目中是否可以使用更大的存储器页面大小来缓存连续页表项的运行。 翻译后备缓冲器可以是其中在每个TLB条目中高速缓存多个页表项的类似MIPS的TLB。

公开(公告)号：US20090070545A1

公开(公告)日：2009-03-12

申请号：US11853451

申请日：2007-09-11

Applicant: Brian Stecher

Inventor： Brian Stecher

IPC: G06F12/08

CPC classification number: G06F12/1036 ,  G06F2212/652

Abstract: A processing system includes memory management software responsive to changes in a page table to consolidate a run of contiguous page table entries into a page table entry having a larger memory page size. The memory management software determines whether the run of contiguous page table entries may be cached using the larger memory page size in an entry of a translation lookaside buffer. The translation lookaside buffer may be a MIPS-like TLB in which multiple page table entries are cached in each TLB entry.

Abstract translation: 处理系统包括响应于页表中的变化的存储器管理软件，以将连续页表项的运行合并到具有较大存储器页大小的页表项中。 存储器管理软件确定在翻译后备缓冲器的条目中是否可以使用更大的存储器页面大小来缓存连续页表项的运行。 翻译后备缓冲器可以是其中在每个TLB条目中高速缓存多个页表项的类似MIPS的TLB。