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    System and method for testing off-chip driver impedance
    1.
    发明授权
    System and method for testing off-chip driver impedance 有权
    用于测试片外驱动器阻抗的系统和方法

    公开(公告)号：US08368422B1

    公开(公告)日：2013-02-05

    申请号：US13463832

    申请日：2012-05-04

    申请人： Bret Roberts Dale ,  Oliver Kiehl

    发明人： Bret Roberts Dale ,  Oliver Kiehl

    IPC分类号： H03K19/00

    CPC分类号： H03K5/1534 ,  H03K19/00346

    摘要： A testing circuit for verifying the impedance of off-chip drivers includes: a plurality of off-chip drivers (OCD), each off-chip driver including a through-silicon via (TSV); an IREF test pad, for driving a current to the plurality of off-chip drivers; a plurality of pre-drivers, each respective pre-driver coupled to one of the plurality of off-chip drivers, wherein the plurality of pre-drivers are configured to turn on the off-chip drivers; a VREF test pad, for inputting a reference voltage to the testing circuit; a plurality of input buffers (IB) for outputting a plurality of comparison results, each of the plurality of input buffers configured to output the plurality of comparison results according to the reference voltage and the voltage at the TSV nodes; and a test pad, coupled to the plurality of IBs, for receiving the comparison results to determine whether the impedance of each OCD is within a desired range.

    摘要翻译： 用于验证片外驱动器的阻抗的测试电路包括：多个芯片外驱动器（OCD），每个芯片外驱动器包括穿硅通孔（TSV）; 用于驱动电流到所述多个芯片外驱动器的IREF测试焊盘; 多个预驱动器，每个相应的预驱动器耦合到所述多个片外驱动器中的一个，其中所述多个预驱动器被配置为导通所述芯片外驱动器; VREF测试板，用于向测试电路输入参考电压; 用于输出多个比较结果的多个输入缓冲器（IB），所述多个输入缓冲器中的每一个被配置为根据所述参考电压和所述TSV节点处的电压输出所述多个比较结果; 以及耦合到所述多个IB的测试焊盘，用于接收所述比较结果，以确定每个OCD的阻抗是否在期望的范围内。

    Data transmission system with reduced power consumption
    4.
    发明授权
    Data transmission system with reduced power consumption 有权
    数据传输系统功耗降低

    公开(公告)号：US07321628B2

    公开(公告)日：2008-01-22

    申请号：US10674859

    申请日：2003-09-30

    申请人： Oliver Kiehl

    发明人： Oliver Kiehl

    IPC分类号： H04L27/00

    CPC分类号： H04L25/4915

    摘要： System and method for reducing power consumption and noise in a transmission system with an asymmetrically terminated transmission line. A preferred embodiment comprises encoding data words to reduce the number of times a given state appears in a code word. The preferred embodiment comprises counting the number of times a given state appears in a data word. If the count is greater than half of the total number of bits in the data word, then the data word is inverted and a weight bit can be set to the given state. If the count is less than (or equal to) half of the total number of bits, then the data word may be unchanged and the weight bit can be set to the inverse of the given state. The code word can be generated by appending the weight bit to the data word.

    摘要翻译： 具有不对称端接传输线的传输系统中降低功耗和噪声的系统和方法。 优选实施例包括编码数据字以减少给定状态在码字中出现的次数。 优选实施例包括对给定状态在数据字中出现的次数进行计数。 如果计数大于数据字中总位数的一半，则数据字被反转，并且可以将权重位设置为给定状态。 如果计数小于（或等于）总位数的一半，则数据字可以不变，并且权重位可以被设置为给定状态的倒数。 可以通过将权重位附加到数据字来生成代码字。

    Memory device and method using a sense amplifier as a cache
    5.
    发明授权
    Memory device and method using a sense amplifier as a cache 有权
    使用读出放大器作为缓存的存储器件和方法

    公开(公告)号：US07215595B2

    公开(公告)日：2007-05-08

    申请号：US10967899

    申请日：2004-10-18

    申请人： Oliver Kiehl

    发明人： Oliver Kiehl

    IPC分类号： G11C8/18

    CPC分类号： G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4094 ,  G11C2207/005

    摘要： A memory device includes a pair of complementary bitlines including a first bitline and a second bitline. A bitline precharge block is coupled between the first bitline and the second bitline. A sense amplifier is coupled to both the first bitline and the second bitline and a sense amplifier precharge block is coupled to the sense amplifier. The sense amplifier precharge block can be activated independently from the bitline precharge block. An isolation block is coupled between the pair of complementary bitlines and the bitline precharge block on one side and the sense amplifier and sense amplifier precharge block on another side.

    摘要翻译： 存储器件包括一对补充位线，包括第一位线和第二位线。 位线预充电块耦合在第一位线和第二位线之间。 读出放大器耦合到第一位线和第二位线，读出放大器预充电块耦合到读出放大器。 读出放大器预充电块可以独立于位线预充电块来激活。 隔离块耦合在一对互补位线和一侧的位线预充电块和另一侧的读出放大器和读出放大器预充电块之间。

    Semiconductor package and method
    6.
    发明授权
    Semiconductor package and method 失效
    半导体封装及方法

    公开(公告)号：US06730989B1

    公开(公告)日：2004-05-04

    申请号：US09596130

    申请日：2000-06-16

    申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

    发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

    IPC分类号： H01L23544

    CPC分类号： H01L23/5382 ,  H01L23/50 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

    摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

    Symmetric clock receiver for differential input signals
    7.
    发明授权
    Symmetric clock receiver for differential input signals 有权
    用于差分输入信号的对称时钟接收器

    公开(公告)号：US06294940B1

    公开(公告)日：2001-09-25

    申请号：US09598349

    申请日：2000-06-21

    申请人： Oliver Kiehl

    发明人： Oliver Kiehl

    IPC分类号： H03K300

    CPC分类号： H03K5/1534 ,  G06F1/10 ,  H03K5/00006

    摘要： A clock circuit, in accordance with the present invention, includes a first circuit stage for providing a first output signal and a second output signal. The first circuit stage includes inputs for clock signals. A switch is coupled to the first stage for switching an output polarity by selecting one of the first output signal and the second output signal generated by the first circuit stage in accordance with a control signal. A second circuit stage is coupled to the first circuit stage through the switch. The second circuit stage for shaping the first and second output signals input thereto from the switch. The second circuit stage includes an output for outputting clock pulses based on the first and second output signals. The control signal is generated from the clock pulses.

    摘要翻译： 根据本发明的时钟电路包括用于提供第一输出信号和第二输出信号的第一电路级。 第一个电路级包括时钟信号的输入。 开关通过根据控制信号选择由第一电路级产生的第一输出信号和第二输出信号之一来耦合到第一级用于切换输出极性。 第二电路级通过开关耦合到第一电路级。 用于对从开关输入的第一和第二输出信号进行整形的第二电路级。 第二电路级包括用于基于第一和第二输出信号输出时钟脉冲的输出。 控制信号由时钟脉冲产生。

    Redundant circuit configuration for an integrated semiconductor memory
    8.
    发明授权
    Redundant circuit configuration for an integrated semiconductor memory 失效
    集成半导体存储器的冗余电路配置

    公开(公告)号：US5657279A

    公开(公告)日：1997-08-12

    申请号：US514602

    申请日：1995-08-14

    申请人： Dominique Savignac ,  Diether Sommer ,  Oliver Kiehl

    发明人： Dominique Savignac ,  Diether Sommer ,  Oliver Kiehl

    IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C8/00

    CPC分类号： G11C29/806 ,  G11C29/812

    摘要： A redundant circuit configuration for an integrated semiconductor memory has normal and redundant memory cells, in which addresses of arbitrary groups of memory cells of the memory are formed from a first partial address and a second partial address. M fixedly programmable address circuits, where M.gtoreq.1, are each assigned to one of the first partial addresses. Each fixedly programmable address circuit in an activated state has the second partial address of a group of normal memory cells to be replaced and has a first output at which an activation signal is applied in the activated state of the address circuit if the first partial address applied to the circuit configuration matches the first partial address assigned to the address circuit. One address comparator is common to all of the address circuits and has a first output. The comparator compares the second partial address stored in memory in one of the address circuits with the applied second partial address, at the applied activation signal of the one address circuit. The comparator supplies an enable signal at the first output of the address comparator if the two partial addresses match. Redundance decoders are triggered by the enable signal.

    摘要翻译： 用于集成半导体存储器的冗余电路配置具有正常和冗余的存储单元，其中存储器的任意存储单元组的地址由第一部分地址和第二部分地址形成。 M个固定可编程地址电路，其中M> / = 1，每个分配给第一部分地址之一。 处于激活状态的每个固定可编程地址电路具有要被替换的一组正常存储器单元的第二部分地址，并且具有第一输出，在第一输出处，如果应用了第一部分地址，则在激活状态下施加激活信号 电路配置匹配分配给地址电路的第一部分地址。 一个地址比较器对于所有地址电路是公共的，并且具有第一输出。 所述比较器在所述一个地址电路的所施加的激活信号上比较存储在其中一个地址电路中的所述第二部分地址与所施加的第二部分地址。 如果两个部分地址匹配，比较器将在地址比较器的第一个输出端提供使能信号。 冗余解码器由使能信号触发。

    CIRCUIT TEST INTERFACE AND TEST METHOD THEREOF
    10.
    发明申请
    CIRCUIT TEST INTERFACE AND TEST METHOD THEREOF 有权
    电路测试接口及其测试方法

    公开(公告)号：US20130082718A1

    公开(公告)日：2013-04-04

    申请号：US13253061

    申请日：2011-10-04

    申请人： Bret Dale ,  Oliver Kiehl

    发明人： Bret Dale ,  Oliver Kiehl

    IPC分类号： G01R1/00

    CPC分类号： G01R31/3172 ,  G01R31/318572

    摘要： A circuit test interface and a test method are disclosed. The circuit test interface may include a test voltage input pad, a test voltage output pad, and a plurality of input buffers. Each of the plurality of input buffers may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of each respective input buffer may be coupled to one of a plurality of through-silicon vias (TSVs). The circuit test interface may further include a plurality of switch units. Each of the plurality of switch units may have a first terminal and a second terminal. The circuit test interface may further include a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad.

    摘要翻译： 公开了电路测试接口和测试方法。 电路测试接口可以包括测试电压输入焊盘，测试电压输出焊盘和多个输入缓冲器。 多个输入缓冲器中的每一个可以具有第一输入端子，第二输入端子和输出端子。 每个相应输入缓冲器的第一输入端可以耦合到多个穿硅通孔（TSV）中的一个。 电路测试接口还可以包括多个开关单元。 多个开关单元中的每一个可以具有第一端子和第二端子。 电路测试接口还可以包括耦合到多个输入缓冲器中的每一个的输出端和测试电压输出焊盘两者的扫描链。