公开(公告)号：US09967120B2

公开(公告)日：2018-05-08

申请号：US15522814

申请日：2015-10-29

Applicant: Benjamin P. Wilkerson

Inventor： Benjamin P. Wilkerson

IPC: H04L27/233

CPC classification number: H04L27/233 ,  H04L27/2331 ,  H04L27/2334

Abstract: A BPSK demodulator circuit comprises: a sideband-separating and lower sideband signal-delaying unit which separates a modulated signal into a lower sideband and an upper sideband by a primary low pass filter and a primary high pass filter having a cut-off frequency as a carrier frequency, and which outputs an upper sideband analog signal and an analog signal delayed by ¼ of a cycle of the carrier frequency from a lower sideband analog signal; a data demodulating unit which demodulates digital data by means of latching, through a hysteresis circuit, an analog pulse signal appearing in accordance with the phase change part of a signal generated by the sum of the analog signals; and a data clock restoring unit which generates a data clock by using a data signal and a signal having the delayed lower sideband analog signal digitized through a comparator.

公开(公告)号：US09860098B2

公开(公告)日：2018-01-02

申请号：US15441946

申请日：2017-02-24

Applicant: Benjamin P. Wilkerson

Inventor： Benjamin P. Wilkerson

IPC: H04L27/233 ,  H04L27/00

CPC classification number: H04L27/2331 ,  H04B1/71637 ,  H04B2201/71636 ,  H04L7/0278 ,  H04L27/0014 ,  H04L27/2334 ,  H04L27/2335 ,  H04L2027/0036

Abstract: An embodiment of the present invention relates to an ultra low power wideband asynchronous binary phase shift keying (BPSK) demodulation method and a circuit configuration thereof. The ultra low power wideband asynchronous BPSK demodulation circuit comprises a sideband division and upper sideband signal delay unit dividing a modulated signal into an upper sideband and a lower sideband by a first order high-pass filter and a first order low-pass filter; a data demodulation unit latching, through a hysteresis circuit, a signal generated by a difference between the analog signals in which a phase difference between the delayed upper sideband analog signal and the lower sideband analog signal is aligned at 0°, so as to demodulate digital data; and a data clock recovery unit for generating a data clock by using a signal digitalized from the lower sideband analog signal through a comparator and a data signal.

公开(公告)号：US10419256B2

公开(公告)日：2019-09-17

申请号：US15519573

申请日：2015-10-15

Applicant: Benjamin P. Wilkerson

Inventor： Benjamin P. Wilkerson

IPC: H04L27/233 ,  H03K5/24 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/096 ,  H04L7/027 ,  H04W4/80

Abstract: An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit; a data demodulation unit; and a data clock restoration unit.