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公开(公告)号：US20240345620A1
公开(公告)日：2024-10-17
申请号：US18634421
申请日：2024-04-12
发明人： Weifeng DONG , Jincai YE , Yuanlin CHENG , Pengfei LIU , Xinxia JIA , Shan LU , Jian WANG
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： A chip, a chip system, and a timestamp synchronization method. The chip is configured to be in communication connection to another chip, and includes a signal generating module, a first signal response module and a first delay module. The signal generating module is configured to generate a synchronization request signal and transmit the synchronization request signal to the first signal response module and the another chip, so that the another chip records a second timestamp of the another chip in response to receiving the synchronization request signal. The first delay module is configured to perform delay processing on the synchronization request signal to obtain a delayed synchronization request signal. The first signal response module is configured to record a first timestamp of the chip in response to receiving the delayed synchronization request signal, wherein the first timestamp and the second timestamp are used for performing a timestamp synchronization operation.
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公开(公告)号：US20240168516A1
公开(公告)日：2024-05-23
申请号：US18513433
申请日：2023-11-17
发明人： Jincai YE , Yuanlin CHENG , Shan LU , Jian WANG
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： A clock synchronization method and apparatus, an electronic device and a storage medium are provided. The clock synchronization method includes: sending a trigger signal to a second processing module and recording a current count value of the first timer upon sending the trigger signal as a first count value; and reading a second count value from the second processing module, the second count value is a current count value of a second timer of the second processing module upon the second processing module receiving the trigger signal, and a count value of the second timer is used as a timing reference of the second processing module and sequentially increasing; the first count value and the second count value are used for a clock compensation to synchronize a first clock domain where the first processing module is located with a second clock domain where the second processing module is located.
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