GENERAL PURPOSE REAL-TIME SAFETY IMPLEMENTATION ON MPU

    公开(公告)号:US20240086238A1

    公开(公告)日:2024-03-14

    申请号:US17932199

    申请日:2022-09-14

    Applicant: Baidu USA LLC

    Abstract: A multiprocessor unit (MPU) in an autonomous driving vehicle (ADV) can provide hard real-time performance. In an embodiment, the MPU can include a hypervisor used to virtualize multiple cores of the MPU, which can further be partitioned into two sets of cores that are isolated from each other. The first set of cores are designated to run real-time related services as trusted applications directly on the hypervisor, and the real-time related services are given higher priority than kernel-level threads on the first set of cores. The second set of cores are designated to run a kernel of an operating system (e.g., Linux). Further, the kernel is patched using a hard real-time open source package to achieve hard real-time performance. An open source package can be used for interprocess communication (IPC) between different electronic control units (ECU) in the ADV.

    HARDWARE ADAPTIVE VEHICLE OS DESIGN ON MCU
    3.
    发明公开

    公开(公告)号:US20240086264A1

    公开(公告)日:2024-03-14

    申请号:US17932203

    申请日:2022-09-14

    Applicant: Baidu USA LLC

    CPC classification number: G06F9/544 G07C5/085

    Abstract: In one embodiment, a vehicle operating system (VOS) that can be partially ported to different types of microcontroller units (MCUs) includes at least one multiprocessor unit (MPU) with an operating system kernel running thereon, and at least one microcontroller unit (MCU) with multiple cores. Each core includes a set of unified application programming interfaces (APIs) for loading one or more MCU drivers corresponding to a type of the MCU, and one or more I/O drivers corresponding to a type of each of the one or more I/O devices associated with the MCU. The set of unified APIs includes at least one API for each service, and can vertically integrate a device path for the service from a hardware layer of the core to the service layer of the core. The VOS further includes multiple pairs of hardware-protected memories associated with each core to enable interprocess communication between the cores.

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