USE OF MULTI-LEVEL MODULATION SIGNALING FOR SHORT REACH DATA COMMUNICATIONS
    2.
    发明申请
    USE OF MULTI-LEVEL MODULATION SIGNALING FOR SHORT REACH DATA COMMUNICATIONS 有权
    使用多级调制信号进行短距离数据通信

    公开(公告)号:US20150146766A1

    公开(公告)日:2015-05-28

    申请号:US14614829

    申请日:2015-02-05

    CPC classification number: H04L25/4917 H04L25/03057 H04L25/03885 H04L27/02

    Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.

    Abstract translation: 短距离通信系统包括多个通信SERDES,其通过短距离信道介质传送数据,例如位于公共PCB上的码片之间的背板连接(例如,PCB轨迹)。 生成多级调制数据信号以通过短距离信道介质发送/接收数据。 诸如四电平PAM的多电平调制数据信号降低数据信号速率,从而降低插入损耗,功率,电路的复杂性以及所需的芯片空间。

    System and method for implementing a single chip having a multiple sub-layer PHY
    3.
    发明授权
    System and method for implementing a single chip having a multiple sub-layer PHY 有权
    用于实现具有多个子层PHY的单个芯片的系统和方法

    公开(公告)号:US08886840B2

    公开(公告)日:2014-11-11

    申请号:US13924082

    申请日:2013-06-21

    CPC classification number: H04B1/40 H04L49/352 H04L49/357

    Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fiber Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.

    Abstract translation: 公开了用于支持10吉比特数字串行通信的系统和方法。 10吉比特数字串行通信收发器模块的许多功能组件和子层可以通过单个芯片使用相同的CMOS技术集成到单个IC芯片中。 单芯片包括PMD发射/接收CMOS子层,PMD PCS CMOS子层,XGXS PCS CMOS子层和XAUI发射/接收CMOS子层。 单芯片支持万兆以太网操作和10千兆位光纤通道操作。 单芯片接口到MAC,光PMD和非易失性存储器。

    SYSTEM AND METHOD FOR IMPLEMENTING A SINGLE CHIP HAVING A MULTIPLE SUB-LAYER PHY
    4.
    发明申请
    SYSTEM AND METHOD FOR IMPLEMENTING A SINGLE CHIP HAVING A MULTIPLE SUB-LAYER PHY 有权
    用于实施具有多个子层PHY的单个芯片的系统和方法

    公开(公告)号:US20130279551A1

    公开(公告)日:2013-10-24

    申请号:US13924082

    申请日:2013-06-21

    CPC classification number: H04B1/40 H04L49/352 H04L49/357

    Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.

    Abstract translation: 公开了用于支持10吉比特数字串行通信的系统和方法。 10吉比特数字串行通信收发器模块的许多功能组件和子层可以通过单个芯片使用相同的CMOS技术集成到单个IC芯片中。 单芯片包括PMD发射/接收CMOS子层,PMD PCS CMOS子层,XGXS PCS CMOS子层和XAUI发射/接收CMOS子层。 单芯片支持万兆以太网操作和10千兆位光纤通道操作。 单芯片接口到MAC,光PMD和非易失性存储器。

Patent Agency Ranking